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参数资料
| 型号： | AD9764-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 18/22页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD9764 |
| 产品培训模块： | DAC Architectures |
| 标准包装： | 1 |
| 系列： | TxDAC® |
| DAC 的数量： | 1 |
| 位数： | 14 |
| 采样率（每秒）： | 125M |
| 数据接口： | 并联 |
| 设置时间： | 35ns |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | 板 |
| 已用 IC / 零件： | AD9764 |
REV. B
AD9764
–5–
PIN CONFIGURATION
14
13
12
11
17
16
15
20
19
18
10
9
8
1
2
3
4
7
6
5
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
AD9764
NC = NO CONNECT
(MSB) DB13
DB12
DB11
DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
CLOCK
DVDD
DCOM
NC
AVDD
COMP2
IOUTA
IOUTB
ACOM
COMP1
FS ADJ
REFIO
REFLO
SLEEP
PIN FUNCTION DESCRIPTIONS
Pin No.
Name
Description
1
DB13
Most Significant Data Bit (MSB).
2–13
DB12–DB1 Data Bits 1–12.
14
DB0
Least Significant Data Bit (LSB).
15
SLEEP
Power-Down Control Input. Active High. Contains active pull-down circuit; it may be left unterminated if
not used.
16
REFLO
Reference Ground when Internal 1.2 V Reference Used. Connect to AVDD to disable internal reference.
17
REFIO
Reference Input/Output. Serves as reference input when internal reference disabled (i.e., Tie REFLO to
AVDD). Serves as 1.2 V reference output when internal reference activated (i.e., Tie REFLO to ACOM).
Requires 0.1
F capacitor to ACOM when internal reference activated.
18
FS ADJ
Full-Scale Current Output Adjust.
19
COMP1
Bandwidth/Noise Reduction Node. Add 0.1
F to AVDD for optimum performance.
20
ACOM
Analog Common.
21
IOUTB
Complementary DAC Current Output. Full-scale current when all data bits are 0s.
22
IOUTA
DAC Current Output. Full-scale current when all data bits are 1s.
23
COMP2
Internal Bias Node for Switch Driver Circuitry. Decouple to ACOM with 0.1
F capacitor.
24
AVDD
Analog Supply Voltage (+2.7 V to +5.5 V).
25
NC
No Internal Connection.
26
DCOM
Digital Common.
27
DVDD
Digital Supply Voltage (+2.7 V to +5.5 V).
28
CLOCK
Clock Input. Data latched on positive edge of clock.
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