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| 型号： | AD9779A-DPG2-EBZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 48/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR AD9779A |
| 设计资源： | Interfacing ADL5370 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0016) Interfacing ADL5371 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0017) Interfacing ADL5372 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0018) Interfacing ADL5373 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0019) Interfacing ADL5374 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0020) Interfacing ADL5375 to AD9779A Dual-Channel, 1 GSPS High Speed DAC (CN0021) AD9788-79A Eval Brd Schematic AD9779A-DPG2-EBZ BOM AD9779A-DPG2-EBZ Gerber Files |
| 标准包装： | 1 |
| 系列： | * |
| DAC 的数量： | 2 |
| 位数： | 16 |
| 采样率（每秒）： | 1G |
| 数据接口： | 串行 |
| DAC 型： | 电流 |
| 工作温度： | -40°C ~ 85°C |
| 已供物品： | * |
| 已用 IC / 零件： | AD9779A |
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AD9776A/AD9778A/AD9779A
Rev. B | Page 52 of 56
0
250
fDATA (MSPS)
PO
W
E
R
(W
)
0.125
25
50
75
100
125
150
175
200
225
2× INTERPOLATION
4× INTERPOLATION
1× INTERPOLATION,
NO MODULATION
8× INTERPOLATION, fDAC/8,
fDAC/4,
fDAC/2,
NO MODULATION
0.100
0.075
0.050
0.025
06
45
2-
0
82
Figure 97. Power Dissipation, Clock 1.8 V Supply, I and Q Data, Dual DAC
Mode, Does Not Include Zero Stuffing
0
250
fDATA (MSPS)
PO
W
E
R
(
W
)
0.075
25
50
75
100
125
150
175
200
225
0.050
0.025
ALL INTERPOLATION MODES
06
45
2-
0
83
Figure 98. Power Dissipation, Digital 3.3 V Supply, I and Q Data,
Dual DAC Mode
0.16
0
1200
fDAC (MSPS)
PO
W
E
R
(
W
)
0.14
0.12
0.10
0.08
0.06
0.04
0.02
200
400
600
800
1000
06
45
2-
0
84
Figure 99. DVDD18 Power Dissipation of Inverse Sinc Filter
POWER-DOWN AND SLEEP MODES
The AD9776A/AD9778A/AD9779A have a variety of power-down
modes; thus, the digital engine, main TxDACs, or auxiliary DACs
can be powered down individually or together. Via the 3-wire
interface port, the main TxDACs can be placed in sleep or power-
down mode. In sleep mode, the TxDAC output is turned off,
thus reducing power dissipation. The reference remains powered
on, however, so that recovery from sleep mode is very fast. With
the power-down mode bit set (Register 0x00, Bit 4), all analog
and digital circuitry, including the reference, is powered down.
The 3-wire interface port remains active in this mode. This
mode offers more substantial power savings than sleep mode,
but the turn-on time is much longer. The auxiliary DACs also
have the capability to be programmed into sleep mode via the
3-wire interface port. The auto power-down enable bit (Register
0x00, Bit 3) controls the power-down function for the digital
section of the devices. The auto power-down function works in
conjunction with the TXENABLE pin (Pin 39); see Table 31 for
details.
Table 31.
TXENABLE
(Pin 39)
Description
0
If auto power-down enable bit = 0, flush data
path with 0s.
If auto power-down enable bit = 1, flush data for
multiple REFCLK cycles; then, automatically
place the digital engine in power-down state.
DACs, reference, and 3-wire interface port are
not affected.
1
Normal operation.
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| AD9779AMOD-EBZ | 制造商:Analog Devices 功能描述:DUAL 16B, 1.0 GSPS TXDAC - Bulk |
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| AD9779BSVZ | 功能描述:IC DAC 16BIT DUAL 1GSPS 100TQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 数模转换器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:1,000 系列:- 设置时间:1µs 位数:8 数据接口:串行 转换器数目:8 电压电源:双 ± 功率耗散（最大）:941mW 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:24-SOIC（0.295"，7.50mm 宽） 供应商设备封装:24-SOIC W 包装:带卷 (TR) 输出数目和类型:8 电压，单极 采样率（每秒）:* |
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