参数资料
型号: AD977ABRSZRL
厂商: Analog Devices Inc
文件页数: 3/24页
文件大小: 0K
描述: IC ADC 16BIT 200KSPS 28SSOP
标准包装: 1,500
位数: 16
采样率(每秒): 200k
数据接口: 串行,SPI?
转换器数目: 1
功率耗散(最大): 100mW
电压电源: 模拟和数字
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 28-SSOP(0.209",5.30mm 宽)
供应商设备封装: 28-SSOP
包装: 带卷 (TR)
输入数目和类型: 3 个单端,单极;3 个单端,双极
配用: EVAL-AD977CB-ND - BOARD EVAL FOR AD977
EVAL-AD977ACB-ND - BOARD EVAL FOR AD977A
AD977/AD977A
–11–
REV. D
EXTERNAL DISCONTINUOUS CLOCK DATA READ
DURING CONVERSION WITH SYNC OUTPUT
GENERATED
Figure 7 illustrates the method by which data from conversion
“n-1” can be read during conversion “n” while using a discon-
tinuous external clock, with the generation of a SYNC output.
What permits the generation of a SYNC output is a transition of
DATACLK while either
CS is High or while both CS and R/C
are low. In Figure 7 a conversion is initiated by taking R/
C low
with
CS tied low. While this condition exists a transition of
DATACLK, clock pulse #0, will enable the generation of a
SYNC pulse. Less then 83 ns after R/
C is taken low the BUSY
output will go low to indicate that the conversion process has
began. Figure 7 shows R/
C then going high and after a delay of
greater than 15 ns (t15) clock pulse #1 can be taken high to
request the SYNC output. The SYNC output will appear
approximately 40 ns after this rising edge and will be valid on
the falling edge of clock pulse #1 and the rising edge of clock
pulse #2. The MSB will be valid approximately 40 ns after the
rising edge of clock pulse #2 and can be latched off either the
falling edge of clock pulse #2 or the rising edge of clock pulse
#3. The LSB will be valid on the falling edge of clock pulse #17
and the rising edge of clock pulse #18. Approximately 40 ns
after the rising edge of clock pulse #18, the DATA output
pin will reflect the state of the TAG input pin during the
rising edge of clock pulse #2.
BUSY
R/C
EXT
DATACLK
t13
BIT 15
(MSB)
BIT 14
12
DATA
SYNC
t14
t12
0
3
17
18
t2
t17
BIT 0
(LSB)
TAG 0
TAG 1
TAG 0
TAG 1
TAG 2
TAG 16
TAG 17
TAG 18
t18
TAG 19
TAG
TAG 2
4
t15
t12
t18
t24
t23
Figure 6. Conversion and Read Timing Using An External Discontinuous Data Clock (EXT/
INT Set to Logic High, CS Set
to Logic Low)
BUSY
R/C
EXT
DATACLK
t13
t15
BIT 15
(MSB)
BIT 14
12
DATA
SYNC
t14
t12
0
318
t1
t12
BIT 0
(LSB)
TAG 0
t22
t15
t
20
t2
t17
t18
Figure 7. Conversion and Read Timing for Reading Previous Conversion Results During a Conversion Using External
Discontinuous Data Clock (EXT/
INT Set to Logic High, CS Set to Logic Low)
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