- 您现在的位置：买卖IC网 > PDF目录10978 > AD9835BRUZ-REEL (Analog Devices Inc)IC DDS 10BIT 50MHZ 16-TSSOP PDF资料下载
参数资料
| 型号： | AD9835BRUZ-REEL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/28页 |
| 文件大小： | 0K |
| 描述： | IC DDS 10BIT 50MHZ 16-TSSOP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 2,500 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 50MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 4.75 V ~ 5.25 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 16-TSSOP |
| 包装： | 带卷 (TR) |
| 配用： | EVAL-AD9835EBZ-ND - BOARD EVALUATION FOR AD9835 |
第1页第2页第3页第4页第5页第6页第7页第8页当前第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
Data Sheet
AD9835
Rev. A | Page 17 of 28
Table 12. Setting SYNC and SELSRC
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
0
SYNC
SELSRC
X1
X1
X1
X1
1 X = don’t care.
Table 13. Power-Down, Resetting and Clearing the AD9835
D15
D14
D13
D12
D11
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
1
SLEEP
RESET
CLR
X1
X1
1 X = don’t care.
Transfer of the data from the 16-bit data register to the
destination register or from the FSELECT/PSEL register to the
respective multiplexer occurs on the next MCLK rising edge.
Because SCLK and MCLK are asynchronous, an MCLK rising
edge may occur while the data bits are in a transitional state.
This can cause a brief spurious DAC output if the register being
written to is generating the DAC output. To avoid such spurious
outputs, the AD9835 contains synchronizing circuitry.
When the SYNC bit is set to 1, the synchronizer is enabled and
data transfers from the serial register (defer register) to the 16-bit
data register, and the FSELECT/PSEL registers occur following
a two-stage pipeline delay that is triggered on the MCLK falling
edge. The pipeline delay ensures that the data is valid when the
transfer occurs. Similarly, selection of the frequency/phase
registers using the FSELECT/PSELx pins is synchronized with
the MCLK rising edge when SYNC = 1. When SYNC = 0, the
synchronizer is bypassed.
Selecting the frequency/phase registers using the pins is
synchronized with MCLK internally also when SYNC = 1 to
ensure that these inputs are valid at the MCLK rising edge. If
times t11 and t11A are met, then the inputs will be at steady state
at the MCLK rising edge. However, if times t11 and t11A are
violated, the internal synchronizing circuitry will delay the
instant at which the pins are sampled, ensuring that the inputs
are valid at the sampling instant (see Figure 5).
LATENCY
Associated with each operation is a latency. When inputs
FSELECT/PSEL change value, there is a pipeline delay before
control is transferred to the selected register; there is a pipeline
delay before the analog output is controlled by the selected
register. When times t11 and t11A are met, PSEL0, PSEL1, and
FSELECT have latencies of six MCLK cycles when SYNC = 0.
When SYNC = 1, the latency is increased to 8 MCLK cycles.
When times t11 and t11A are not met, the latency can increase by
one MCLK cycle. Similarly, there is a latency associated with
each write operation. If a selected frequency/phase register is
loaded with a new word, there is a delay of 6 to 7 MCLK cycles
before the analog output will change (there is an uncertainty of
one MCLK cycle regarding the MCLK rising edge at which the
data is loaded into the destination register). When SYNC = 1,
the latency is 8 or 9 MCLK cycles.
FLOWCHARTS
The flowchart in Figure 22 shows the operating routine for the
reset, which resets the phase accumulator to zero so that the
analog output is at midscale. To avoid spurious DAC outputs
while the AD9835 is being initialized, the RESET bit should be
set to 1 until the part is ready to begin generating an output.
Taking CLR high sets SYNC and SELSRC to 0 so that the
FSELECT/PSELx pins are used to select the frequency/phase
registers, and the synchronization circuitry is bypassed. A write
operation is needed to the SYNC/SELSRC register to enable the
synchronization circuitry or to change control to the FSELECT/
PSEL bits.
RESET does not reset the phase and frequency registers. These
registers will contain invalid data and, therefore, should be set to
a known value by the user. The RESET bit is then set to 0 to begin
generating an output. A signal will appear at the DAC output 6
MCLK cycles after RESET is set to 0.
The analog output is fMCLK/232 × FREG, where FREG is the value
loaded into the selected frequency register. This signal is phase
shifted by the amount specified in the selected phase register
(2π/4096 × PHASEx REG, where PHASEx REG is the value
contained in the selected phase register).
Control of the frequency/phase registers can be interchanged
from the pins to the bits.
相关PDF资料 |
PDF描述 |
|---|---|
| VE-BWX-IX-B1 | CONVERTER MOD DC/DC 5.2V 75W |
| VI-B1F-IX-B1 | CONVERTER MOD DC/DC 72V 75W |
| VI-B1F-IW-B1 | CONVERTER MOD DC/DC 72V 100W |
| VI-B1D-IW-B1 | CONVERTER MOD DC/DC 85V 100W |
| VI-B1B-IW-B1 | CONVERTER MOD DC/DC 95V 100W |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9835BRUZ-REEL7 | 功能描述:IC DDS 10BIT 50MHZ 16-TSSOP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9835EB | 制造商:AD 制造商全称:Analog Devices 功能描述:Evaluation Board for the AD9835 Direct Digital Synthesizer |
| AD9837 | 制造商:AD 制造商全称:Analog Devices 功能描述:Low Power, 8.5 mW, 2.3 V to 5.5 V, Programmable Waveform Generator |
| AD9837ACPZ-RL | 功能描述:IC WAVEFORM GEN PROG 10LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9837ACPZ-RL7 | 功能描述:IC WAVEFORM GEN PROG 10LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
发布紧急采购，3分钟左右您将得到回复。