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| 型号： | AD9838ACPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/32页 |
| 文件大小： | 0K |
| 描述： | IC DDS 16MHZ LOW PWR 20LFCSP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1,500 |
| 分辨率（位）： | 10 b |
| 主 fclk： | 5MHz |
| 电源电压： | 2.3 V ~ 5.5 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 20-LFCSP-WQ（4x4） |
| 包装： | 带卷 (TR) |
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AD9838
Rev. A | Page 18 of 32
Table 7. Control Register Bit Descriptions
Bit
Bit Name
Description
D13
B28
Two write operations are required to load a complete word into either of the frequency registers.
B28 = 1 allows a complete word to be loaded into a frequency register in two consecutive writes. The first write
contains the 14 LSBs of the frequency word, and the second write contains the 14 MSBs. The first two bits of each
16-bit word define the frequency register to which the word is loaded and should, therefore, be the same for both
consecutive writes. See Table 11 for the appropriate addresses. The write to the frequency register occurs after both
words have been loaded, so the register never holds an intermediate value. An example of a complete 28-bit write
is shown in Table 12. Note, however, that consecutive 28-bit writes to the same frequency register are not allowed;
to execute consecutive 28-bit writes, you must alternate between the frequency registers.
B28 = 0 configures the 28-bit frequency register to operate as two 14-bit registers, one containing the 14 MSBs and
the other containing the 14 LSBs. In this way, the 14 MSBs of the frequency word can be altered independently of
the 14 LSBs, and vice versa. To alter the 14 MSBs or the 14 LSBs, a single write is made to the appropriate frequency
address. Bit D12 (HLB) informs the AD9838 whether the bits to be altered are the 14 MSBs or the 14 LSBs.
D12
HLB
This control bit allows the user to continuously load the MSBs or LSBs of a frequency register while ignoring the
remaining 14 bits. This is useful if the complete 28-bit resolution is not required. The HLB bit is used in conjunction
with the B28 bit (Bit D13). The HLB bit indicates whether the 14 bits to be loaded are transferred to the 14 MSBs or
the 14 LSBs of the addressed frequency register. Bit D13 (B28) must be set to 0 to change the MSBs or LSBs of a
frequency word separately. When Bit D13 (B28) is set to 1, the HLB bit is ignored.
HLB = 1 allows a write to the 14 MSBs of the addressed frequency register.
HLB = 0 allows a write to the 14 LSBs of the addressed frequency register.
D11
FSEL
The FSEL bit defines whether the FREQ0 register or the FREQ1 register is used in the phase accumulator (see Table 9).
D10
PSEL
The PSEL bit defines whether the PHASE0 register data or the PHASE1 register data is added to the output of the
phase accumulator (see Table 10).
D9
PIN/SW
The following functions can be implemented using either software or hardware: frequency register selection, phase
register selection, reset of internal registers, and DAC power-down. The PIN/SW bit selects the source of control for
these functions.
PIN/SW = 1 selects the control pins to implement the register selection, reset, and DAC power-down functions.
PIN/SW = 0 selects the control bits to implement the register selection, reset, and DAC power-down functions.
D8
RESET
When the PIN/SW bit is set to 0, this bit controls the reset function.
RESET = 1 resets internal registers to 0, which corresponds to an analog output of midscale.
RESET = 0 disables the reset function (see the Reset Function section).
D7
SLEEP1
This bit enables or disables the internal MCLK.
SLEEP1 = 1 disables the internal MCLK. The DAC output remains at its present value because the NCO is no longer
accumulating.
SLEEP1 = 0 enables the internal MCLK (see the Sleep Function section).
D6
SLEEP12
When the PIN/SW bit is set to 0, this bit powers down the on-chip DAC.
SLEEP12 = 1 powers down the on-chip DAC. This is useful when the AD9838 is used to output the MSB of the DAC data.
SLEEP12 = 0 implies that the DAC is active (see the Sleep Function section).
D5
OPBITEN
This bit controls whether an output is available at the SIGN BIT OUT pin. If the user is not using the SIGN BIT OUT
pin, this bit should be set to 0.
OPBITEN = 1 enables the SIGN BIT OUT pin.
OPBITEN = 0 places the SIGN BIT OUT output buffer into a high impedance state (no output is available at the SIGN
BIT OUT pin).
D4
SIGN/PIB
This bit controls the output at the SIGN BIT OUT pin when the OPBITEN bit (Bit D5) is set to 1.
SIGN/PIB = 1 connects the on-board comparator to the SIGN BIT OUT pin. After filtering the sinusoidal output from
the DAC, the waveform can be applied to the comparator to generate a square waveform (see Table 18).
SIGN/PIB = 0 connects the MSB (or MSB/2) of the DAC data to the SIGN BIT OUT pin. Bit D3 (DIV2) controls whether
the output is the MSB or MSB/2.
D3
DIV2
DIV2 is used when the OPBITEN bit (Bit D5) is set to 1 and the SIGN/PIB bit (Bit D4) is set to 0 (see Table 18).
DIV2 = 1 causes the MSB of the DAC data to be output at the SIGN BIT OUT pin.
DIV2 = 0 causes the MSB/2 of the DAC data to be output at the SIGN BIT OUT pin.
D2
Reserved
This bit must be set to 0.
D1
MODE
This bit, in association with the OPBITEN bit (Bit D5), controls the output at the IOUT and IOUTB pins. This bit should
be set to 0 if the OPBITEN bit is set to 1 (see Table 19).
MODE = 1 bypasses the SIN ROM, resulting in a triangle output from the DAC.
MODE = 0 uses the SIN ROM to convert the phase information into amplitude information, resulting in a sinusoidal
signal at the output.
D0
Reserved
This bit must be set to 0.
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