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参数资料
| 型号： | AD9878 |
| 厂商： | Analog Devices, Inc. |
| 元件分类： | 开关 |
| 英文描述： | Mixed-Signal Front End for Broadband Applications |
| 中文描述： | 混合信号的宽带应用前端 |
| 文件页数： | 17/36页 |
| 文件大小： | 749K |
| 代理商： | AD9878 |
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AD9878
Setting this bit to 0 (default) configures the serial interface to be
compatible with AD8321/AD8323/AD8328 variable cable gain
amplifiers. Setting this bit to 1 configures the serial interface to be
compatible with AD8322/AD8327 variable cable gain amplifiers.
Bit 5: Profile Select
The AD9878 quadrature digital upconverter can store two
preconfigured modulation modes, called profiles. Each profile
defines a transmit FTW cable-driver amplifier gain setting, and
DAC gain setting. The profile select bit or PROFILE pin programs
the current register profile to be used. If the PROFILE pin is used
to switch between profiles, the profile select bit should be set to 0
and tied low.
Rev. A | Page 17 of 36
REGISTERS 0x10 THROUGH 0x17—
BURST PARAMETER
Tx Frequency Tuning Words
The FTW determines the DDS-generated carrier frequency (f
C
)
and is formed via a concatenation of register addresses.
The 26-bit FTW is spread over four register addresses. Bit 25 is
the MSB, and Bit 0 is the LSB. The carrier frequency equation is
as follows:
(
2
SYSCLK
C
f
FTW
f
)
26
×
=
Where
2000
x
0
and
,
<
×
=
FTW
f
M
f
OSCIN
SYSCLK
.
Changes to FTW bytes take effect immediately.
Cable-Driver Gain Control
The AD9878 has a 3-pin interface to the AD832x family of
programmable gain cable-driver amplifiers. This allows direct
control of the cable driver’s gain through the AD9878. In its
default mode, the complete 8-bit register value is transmitted
over the 3-wire cable amplifier (CA) interface.
If Bit 3 of Register 0x0F is set high, Bits [7:4] of Register 0x13
and Register 0x17 determine the 8-bit word sent over the CA
interface, according to the specifications in Table 6. Bits [3:0] of
Register 0x13 and Register 0x17 determine the fine gain setting
of the DAC output, according to specifications in Table 7.
Table 6. Cable-Driver Gain Control
Bits [7:4]
CA Interface Transmit Word
0000
0000 0000 (default)
0001
0000 0001
0010
0000 0010
0011
0000 0100
0100
0000 1000
0101
0001 0000
0110
0010 0000
0111
0100 0000
1000
1000 0000
Table 7. DAC Output Fine Gain Setting
Bits [3:0]
0000
0001
0010
0011
…
1110
1111
DAC Fine Gain (dB)
0.0 (default)
0.5
1.0
1.5
…
7.0
7.5
New data is automatically sent over the 3-wire CA interface
(and DAC gain adjust) whenever the value of the active gain
control register changes or a new profile is selected. The default
value is 0x00 (lowest gain).
The formula for the combined output-level calculation of
AD9878 fine gain and AD8327 or AD8322 coarse gain is:
(
)
0
9878
8327
fine
V
V
(
)
0
9878
8322
fine
V
V
( )
(
)
19
2
+
+
=
coarse
( )
(
)
14
2
+
+
=
coarse
where:
fine
is the decimal value of Bits [3:0].
coarse
is the decimal value of Bits [7:4].
V
9878(0)
is the level at AD9878 output in dBmV for fine = 0.
V
8327
is the level at output of AD8327 in dBmV.
V
8322
is the level at output of AD8322 in dBmV.
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| AD9878BST | Mixed-Signal Front End for Broadband Applications |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9878BST | 制造商:Analog Devices 功能描述:Mixed Signal Front End 100-Pin LQFP |
| AD9878BSTRL | 制造商:Analog Devices 功能描述:Mixed Signal Front End 100-Pin LQFP T/R 制造商:Analog Devices 功能描述:MIXED SGNL FRONT END 100LQFP - Tape and Reel |
| AD9878BSTZ | 功能描述:IC FRONT-END MIXED-SGNL 100-LQFP RoHS:是 类别:集成电路 (IC) >> 数据采集 - 模拟前端 (AFE) 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:2,500 系列:- 位数:- 通道数:2 功率（瓦特）:- 电压 - 电源，模拟:3 V ~ 3.6 V 电压 - 电源，数字:3 V ~ 3.6 V 封装/外壳:32-VFQFN 裸露焊盘 供应商设备封装:32-QFN（5x5） 包装:带卷 (TR) |
| AD9878-EB | 制造商:Analog Devices 功能描述:EVAL KIT FOR MIXED-SGNL FRONT END FOR BROADBAND APPLICATIONS - Bulk |
| AD9879 | 制造商:AD 制造商全称:Analog Devices 功能描述:Mixed-Signal Front End Set-Top Box, Cable Modem |
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