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| 型号： | AD9949AKCPZRL |
| 厂商： | Analog Devices Inc |
| 文件页数： | 19/36页 |
| 文件大小： | 0K |
| 描述： | IC CCD SIGNAL PROCESSOR 40-LFCSP |
| 标准包装： | 2,500 |
| 类型： | CCD 信号处理器，12 位 |
| 输入类型： | 逻辑 |
| 输出类型： | 逻辑 |
| 接口： | 3 线串口 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 40-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 40-LFCSP |
| 包装： | 带卷 (TR) |
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AD9949
Rev. B | Page 26 of 36
ANALOG FRONT END DESCRIPTION AND OPERATION
The AD9949 signal processing chain is shown in Figure 28.
Each processing step is essential in achieving a high quality
image from the raw CCD pixel data.
DC RESTORE
To reduce the large dc offset of the CCD output signal, a dc
restore circuit is used with an external 0.1 F series coupling
capacitor. This restores the dc level of the CCD signal to
approximately 1.5 V to be compatible with the 3 V supply
voltage of the AD9949.
CORRELATED DOUBLE SAMPLER
The CDS circuit samples each CCD pixel twice to extract the
video information and reject low frequency noise. The timing
shown in Figure 17 illustrates how the two internally generated
CDS clocks, SHP and SHD, are used to sample the reference
level and the CCD signal level, respectively. The placement of
the SHP and SHD sampling edges is determined by the setting
of the SAMPCONTROL register located at Address 0×63.
Placement of these two clock signals is critical in achieving the
best performance from the CCD.
The gain in the CDS is fixed at 0 dB by default. Using Bits D10
and D11 in the AFE operation register, the gain may be reduced
to 2 dB or 4 dB. This allows the AD9949 to accept an input
signal of greater than 1 V p-p. See Table 14 for register details.
Table 22. Adjustable CDS Gain
Operation Register Bits
D11
D10
CDS Gain
Max CDS Input
0
0 dB
1.0 V p-p
0
1
2 dB
1.2 V p-p
1
0
4 dB
1.6 V p-p
1
0 dB
1.0 V p-p
PxGA
The PxGA provides separate gain adjustment for the individual
color pixels. A programmable gain amplifier with four separate
values, the PxGA has the capability to multiplex its gain value
on a pixel-to-pixel basis (see Figure 29). This allows lower
output color pixels to be gained up to match higher output color
pixels. Also, the PxGA may be used to adjust the colors for
white balance, reducing the amount of digital processing that
is needed. The four different gain values are switched according
to the color steering circuitry. Three different color steering
modes for different types of CCD color filter arrays are
programmable in the AFE CTLMODE register at Address 0×03
(see Figure 33 to Figure 35 for timing examples). For example,
progressive steering mode accommodates the popular Bayer
arrangement of red, green, and blue filters (see Figure 30).
6dB ~ 42dB
CCDIN
DIGITAL
FILTER
CLPOB
DC RESTORE
OPTICAL BLACK
CLAMP
12-BIT
ADC
VGA
DAC
8
CDS
INTERNAL
VREF
2V FULL SCALE
0dB ~ 18dB
SHP
SHD
PxGA
1.5V
OUTPUT
DATA
LATCH
REFT
REFB
DOUT
PHASE
SHP
SHD
DOUT
PHASE
CLPOB PBLK
PBLK
1.0V
2.0V
DOUT
AD9949
0dB, –2dB, –4dB
1.0
F 1.0F
1.0
F
03751-029
PxGA GAIN
REGISTERS
VGA GAIN
REGISTER
CLAMP LEVEL
REGISTER
12
V-H
TIMING
GENERATION
PRECISION
TIMING
GENERATION
Figure 28. Analog Front End Functional Block Diagram
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| AD9949BCBZRL | 制造商:Analog Devices 功能描述: |
| AD9949KCP | 制造商:Analog Devices 功能描述:AFE Video 1ADC 12-Bit 3V 40-Pin LFCSP EP 制造商:Rochester Electronics LLC 功能描述:12 BIT 36 MSPS, 3 V ANALOG FRONT END - Bulk |
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| AD9949KCPZ | 功能描述:IC CCD SIGNAL PROCESSOR 40-LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 传感器和探测器接口 系列:- 其它有关文件:Automotive Product Guide 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:74 系列:- 类型:触控式传感器 输入类型:数字 输出类型:数字 接口:JTAG，串行 电流 - 电源:100µA 安装类型:表面贴装 封装/外壳:20-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:20-TSSOP 包装:管件 |
| AD9949KCPZRL | 功能描述:IC CCD SIGNAL PROCESSOR 40-LFCSP RoHS:是 类别:集成电路 (IC) >> 接口 - 传感器和探测器接口 系列:- 其它有关文件:Automotive Product Guide 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:74 系列:- 类型:触控式传感器 输入类型:数字 输出类型:数字 接口:JTAG，串行 电流 - 电源:100µA 安装类型:表面贴装 封装/外壳:20-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:20-TSSOP 包装:管件 |
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