- 您现在的位置：买卖IC网 > PDF目录10979 > AD9952YSVZ (Analog Devices Inc)IC DDS 14BIT DAC 1.8V 48-TQFP PDF资料下载
参数资料
| 型号： | AD9952YSVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/28页 |
| 文件大小： | 0K |
| 描述： | IC DDS 14BIT DAC 1.8V 48-TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 400MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.71 V ~ 1.96 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP 裸露焊盘 |
| 供应商设备封装： | 48-TQFP 裸露焊盘（7x7） |
| 包装： | 托盘 |
| 产品目录页面： | 552 (CN2011-ZH PDF) |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页当前第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页
AD9952
Rev. B | Page 19 of 28
The shaped on-off keying function can be bypassed (disabled)
by clearing the OSK enable bit (CFR1 [25] = 0).
The modes are controlled by two bits located in the most
significant byte of the control function register (CFR). CFR1
[25] is the shaped on-off keying enable bit. When CFR1 [25] is
set, the output scaling function is enabled and CFR1 [25]
bypasses the function. CFR1 [24] is the internal shaped on-off
keying active bit. When CFR1 [24] is set, internal shaped on-off
keying mode is active; when CFR1 [24] is cleared, external
shaped on-off keying mode is active. CFR1 [24] is a don’t care if
the shaped on-off keying enable bit (CFR1 [25]) is cleared. The
power-up condition of the shaped on-off keying is disabled
(CFR1 [25] = 0). Figure 23 shows the block diagram of the OSK
circuitry.
Auto Shaped On-Off Keying Mode Operation
The auto shaped on-off keying mode is active when CFR1 [25]
and CFR1 [24] are set. When auto shaped on-off keying mode is
enabled, a single-scale factor is internally generated and applied
to the multiplier input for scaling the output of the DDS core
block (see Figure 23). The scale factor is the output of a 14-bit
counter that increments/decrements at a rate determined by the
contents of the 8-bit output ramp rate register. The scale factor
increases if the OSK pin is high and decreases if the OSK pin is
low. The scale factor is an unsigned value such that all 0s
multiply the DDS core output by 0 (decimal) and 0x3FFF
multiplies the DDS core output by 16,383 (decimal).
To use the full amplitude (14-bits) with fast ramp rates, the
internally generated scale factor step size is controlled via the
ASF [15:14]. Table 6 describes the increment/decrement step
size of the internally generated scale factor per the ASF [15:14].
A special feature of this mode is that the maximum output
amplitude allowed is limited by the contents of the amplitude
scale factor register. This allows the user to ramp to a value less
than full scale.
Table 6. Auto Scale Factor Internal Step Size
ASF [15:14] (Binary)
Increment/Decrement Size
00
1
01
2
10
4
11
8
OSK Ramp Rate Timer
The OSK ramp rate timer is a loadable down counter that
generates the clock signal to the 14-bit counter, which, in turn,
generates the internal scale factor. The ramp rate timer is loaded
with the value of the ASFR every time the counter reaches 1
(decimal). This load and countdown operation continues for as
long as the timer is enabled, unless the timer is forced to load
before reaching a count of 1.
If the load OSK timer bit (CFR1 [26]) is set, the ramp rate timer
is loaded upon an I/O UPDATE or upon reaching a value of 1.
The ramp timer can be loaded before reaching a count of 1 by
three methods.
The first method of loading is by changing the OSK input pin.
When the OSK input pin changes state, the ASFR value is
loaded into the ramp rate timer, which then proceeds to count
down as normal.
The second method in which the sweep ramp rate timer can be
loaded before reaching a count of 1 is if the load OSK timer bit
(CFR1 [26]) is set and an I/O UPDATE is issued.
The last method in which the sweep ramp rate timer can be
loaded before reaching a count of 1 is when going from the
inactive auto shaped on-off keying mode to the active auto
shaped on-off keying mode; that is, when the sweep enable bit is
being set.
OSK PIN
LOAD OSK TIMER
CFR1[26]
SYNC_CLK
AUTO DESK
ENABLE
CFR1[24]
TO DAC
AUTO SCALE
FACTOR GENERATOR
RAMP RATE TIMER
CLOCK
DDS CORE
OSK ENABLE
CFR[25]
AMPLITUDE SCALE
FACTOR REGISTER
(ASF)
0
1
01
HOLD
INC/DEC ENABLE
OUT
COS(X)
AMPLITUDE RAMP
RATE REGISTER
(ASF)
UP/DN
DATA
LOAD
EN
03
35
8-
0
23
Figure 23. On-Off Shaped Keying, Block Diagram
相关PDF资料 |
PDF描述 |
|---|---|
| MC9S08DZ96MLF | MCU 8BIT 96K FLASH 48-LQFP |
| AD5933YRSZ | IC NTWK ANALYZER 12B 1MSP 16SSOP |
| MC908JL3EMPE | IC MCU 4K FLASH W/OSC 28-PDIP |
| MC908AP8CFAE | IC MCU 8K FLASH 8MHZ 48-LQFP |
| AD9851BRSZ | IC SYNTHESIZER DDS/DAC 28-SSOP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9952YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9952 TQFP48 |
| AD9952YSVZ-REEL7 | 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9953 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9953/PCB | 制造商:Analog Devices 功能描述:400 MSPS, 14BIT DGTL SYNTHESIZER - Bulk |
| AD9953ASV | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
发布紧急采购，3分钟左右您将得到回复。