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| 型号： | AD9952YSVZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 13/28页 |
| 文件大小： | 0K |
| 描述： | IC DDS 14BIT DAC 1.8V 48-TQFP |
| 产品培训模块： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 标准包装： | 1 |
| 分辨率（位）： | 14 b |
| 主 fclk： | 400MHz |
| 调节字宽（位）： | 32 b |
| 电源电压： | 1.71 V ~ 1.96 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP 裸露焊盘 |
| 供应商设备封装： | 48-TQFP 裸露焊盘（7x7） |
| 包装： | 托盘 |
| 产品目录页面： | 552 (CN2011-ZH PDF) |
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AD9952
Rev. B | Page 20 of 28
External Shaped On-Off Keying Mode Operation
The external shaped on-off keying mode is enabled by writing
CFR1 [25] to a Logic 1 and writing CFR1 [24] to a Logic 0. When
configured for external shaped on-off keying, the content of the
ASFR becomes the scale factor for the data path. The scale factors
are synchronized to SYNC_CLK via the I/O UPDATE
functionality.
SYNCHRONIZING MULTIPLE AD9952s
The AD9952 product allows easy synchronization of multiple
AD9952s. There are three modes of synchronization available to
the user: an automatic synchronization mode, a software
controlled manual synchronization mode, and a hardware
controlled manual synchronization mode. In all cases, to
synchronize two or more devices, the following considerations
must be observed. First, all units must share a common clock
source. Trace lengths and path impedance of the clock tree must
be designed to keep the phase delay of the different clock
branches as closely matched as possible. Second, the I/O
UPDATE signal’s rising edge must be provided synchronously
to all devices in the system. Finally, regardless of the internal
synchronization method used, the DVDD_I/O supply should
be set to 3.3 V for all devices that are to be synchronized.
AVDD and DVDD should be left at 1.8 V.
In automatic synchronization mode, one device is chosen as a
master; the other devices are slaved to this master. When
configured in this mode, the slaves automatically synchronize their
internal clocks to the SYNC_CLK output signal of the master
device. To enter automatic synchronization mode, set the slave
device’s automatic synchronization bit (CFR1 [23] = 1). Connect
the SYNC_IN input(s) to the master SYNC_CLK output. The
slave device continuously updates the phase relationship of its
SYNC_CLK until it is in phase with the SYNC_IN input, which
is the SYNC_CLK of the master device. When attempting to
synchronize devices running at SYSCLK speeds beyond 250 MSPS,
the high speed sync enhancement enable bit should be set (CFR2
[11] = 1).
In software manual synchronization mode, the user forces the
device to advance the SYNC_CLK rising edge one SYSCLK cycle
( SYNC_CLK period). To activate the manual synchronization
mode, set the slave device’s software manual synchronization bit
(CFR1 [22] = 1). The bit (CFR1 [22]) is cleared immediately. To
advance the rising edge of the SYNC_CLK multiple times, this bit
needs to be set multiple times.
In hardware manual synchronization mode, the SYNC_IN input
pin is configured such that it advances the rising edge of the
SYNC_CLK signal each time the device detects a rising edge on
the SYNC_IN pin. To put the device into hardware manual
synchronization mode, set the hardware manual synchronization
bit (CFR2 [10] = 1). Unlike the software manual synchronization
bit, this bit does not self-clear.
Once the hardware manual synchronization mode is enabled, all
rising edges detected on the SYNC_IN input cause the device to
advance the rising edge of the SYNC_CLK by one SYSCLK cycle
until this enable bit is cleared (CFR2 [10] = 0).
Using a Single Crystal to Drive Multiple AD9952 Clock
Inputs
The AD9952 crystal oscillator output signal is available on the
CRYSTAL OUT pin, enabling one crystal to drive multiple
AD9952s. To drive multiple AD9952s with one crystal, the
CRYSTAL OUT pin of the AD9952 using the external crystal
should be connected to the REFCLK input of the other AD9952.
The CRYSTAL OUT pin is static until the CFR2 [9] bit is set,
enabling the output. The drive strength of the CRYSTAL OUT
pin is typically very low, so this signal should be buffered prior
to using it to drive any loads.
SERIAL PORT OPERATION
The operations of the AD9952 are controlled by setup data and
parameters loaded into the device by means of a serial I/O port.
The internal control structure is organized as a series of
registers. Each register is double-buffered. New data is first
stored in I/O buffers as it is received. Subsequently, the data is
transferred to the internal registers that actually control the
device operation. While the I/O buffers are receiving new data,
the old data that is already in the control registers continues to
be used until the I/O buffers are transferred into the control
registers. The transfer from I/O buffer to control registers
requires an I/O update event. This event is triggered by sending
a pulse to the I/O UPDATE pin.
Step 1: Writing Data Through the Serial I/O Port to the
I/O Buffers
There are two phases to a serial I/O communication cycle:
Phase 1: Instruction (one byte)
Phase 2: Data (one or more bytes)
Phase 1 is the instruction byte, clocked in by the first eight
rising edges of SCLK. This single byte provides the AD9952
serial port controller with the information that it needs
regarding the upcoming data phase, Phase 2. This information
tells the serial port controller whether the data is a read or a
write operation, as well as the address of the intended register.
Once the controller knows the register address, the number of
bytes of data to be expected is calculated automatically.
The number of bytes transferred during Phase 2 depends on the
particular register being accessed. For example, when the Control
Function Register 2 is accessed, the data consists of three bytes (or
24 bits). However, if the Frequency Tuning Word 0 register is
accessed, the data is four bytes (or 32 bits). Step 1 is complete
when both the instruction byte and the required number of data
bytes are written to or read from.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| AD9952YSVZ | 制造商:Analog Devices 功能描述:IC DDS 400MSPS SMD 9952 TQFP48 |
| AD9952YSVZ-REEL7 | 功能描述:IC DDS DAC 14BIT 1.8V 48TQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 直接数字合成 (DDS) 系列:- 产品变化通告:Product Discontinuance 27/Oct/2011 标准包装:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 调节字宽（位）:32 b 电源电压:2.97 V ~ 5.5 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-TSSOP（0.173"，4.40mm 宽） 供应商设备封装:16-TSSOP 包装:带卷 (TR) |
| AD9953 | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
| AD9953/PCB | 制造商:Analog Devices 功能描述:400 MSPS, 14BIT DGTL SYNTHESIZER - Bulk |
| AD9953ASV | 制造商:AD 制造商全称:Analog Devices 功能描述:400 MSPS 14-Bit, 1.8V CMOS Direct Digital Synthesizer |
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