参数资料
型号: AD9957BSVZ
厂商: Analog Devices Inc
文件页数: 15/64页
文件大小: 0K
描述: IC DDS 1GSPS 14BIT IQ 100TQFP
产品培训模块: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
标准包装: 1
分辨率(位): 14 b
主 fclk: 1GHz
调节字宽(位): 32 b
电源电压: 1.8V, 3.3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-TQFP 裸露焊盘
供应商设备封装: 100-TQFP-EP(14x14)
包装: 托盘
产品目录页面: 552 (CN2011-ZH PDF)
配用: AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD
AD9957
Data Sheet
Rev. C | Page 22 of 64
tDH
I0
TxENABLE
PDCLK
D<17:0>
IK
IK – 1
I3
I2
I1
06384-
010
tDH
tDS
Figure 30. 18-Bit Parallel Port Timing Diagram—Interpolating DAC Mode
tDH
I0
TxENABLE
PDCLK
D<17:0>
QN
IN
Q1
I1
Q0
06384-
0
1
tDH
tDS
Figure 31. 18-Bit Parallel Port Timing Diagram—Quadrature Modulation Mode
TxENABLE
PDCLK
I DATA
Q DATA
Q0
Q1
Q2
Q3
Q4
Q6
Q5
Q7
Q8
Q9
Q10
Q11
Q12
Q13
Q14
Q15
I0
I1
I2
I3
I4
I6
I5
I7
I8
I9
I10
I11
I12
I13
I14
I15
I16n – 1
Q16n – 1
06384-
012
Figure 32. Dual Serial I/Q Bit Stream Timing Diagram, BFI Mode
INPUT DATA ASSEMBLER
The input to the AD9957 is an 18-bit parallel data port in
QDUC mode or interpolating DAC mode. In BFI mode, it
operates as a dual serial data port.
In QDUC mode, it is assumed that two consecutive 18-bit
words represent the real (I) and imaginary (Q) parts of a
complex number of the form, I + jQ. The 18-bit words are
supplied to the input of the AD9957 at a rate of
R
f
SYSCLK
PDCLK
2
=
for QDUC mode
where:
fSYSCLK (for all of the PDCLK equations in this section) is the
sample rate of the DAC.
R (for all of the PDCLK equations in this section) is the
interpolation factor of the programmable interpolation filter.
When the PDCLK rate control bit is active in QDUC mode,
however, the frequency of PDCLK becomes
R
f
SYSCLK
PDCLK
4
=
with PDCLK rate control active
In the interpolating DAC mode, the rate of PDCLK is the same
as QDUC mode with the PDCLK rate control bit active, that is,
R
f
SYSCLK
PDCLK
4
=
for interpolating DAC mode
In BFI mode, the 18-bit parallel input converts to a dual serial
input that is, one pin is assigned as the serial input for the I-words
and one pin is assigned as the serial input for the Q-words. The
other 16 pins are not used. Furthermore, each I- and Q-word
has a 16-bit resolution. fPDCLK is the bit rate of the I- and Q-data
streams and is given by
R
f
SYSCLK
PDCLK =
for BFI mode
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