参数资料
型号: AD9957BSVZ
厂商: Analog Devices Inc
文件页数: 8/64页
文件大小: 0K
描述: IC DDS 1GSPS 14BIT IQ 100TQFP
产品培训模块: Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
标准包装: 1
分辨率(位): 14 b
主 fclk: 1GHz
调节字宽(位): 32 b
电源电压: 1.8V, 3.3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 100-TQFP 裸露焊盘
供应商设备封装: 100-TQFP-EP(14x14)
包装: 托盘
产品目录页面: 552 (CN2011-ZH PDF)
配用: AD9957/PCBZ-ND - BOARD EVAL AD9957 QUADRATURE MOD
AD9957
Data Sheet
Rev. C | Page 16 of 64
MODES OF OPERATION
OVERVIEW
The AD9957 has three basic operating modes.
Quadrature modulation (QDUC) mode (default)
Interpolating DAC mode
Single tone mode
The active mode is selected via the operating mode bits in
Control Function Register 1 (CFR1). Single tone mode allows
the device to operate as a sinusoidal generator with the DDS
driving the DAC directly.
Interpolating DAC mode bypasses the DDS, allowing the user
to deliver baseband data to the device at a sample rate lower
than that of the DAC. An internal chain of rate interpolation
filters the user data and upsamples to the DAC sample rate.
Combined, the filters provide for programmable rate interpola-
tion while suppressing spectral images and retaining the original
baseband spectrum.
QDUC mode employs both the DDS and the rate interpolation
filters. In this case, two parallel banks of rate interpolation
filters allow baseband processing of in-phase and quadrature
(I/Q) signals with the DDS providing the carrier signal to be
modulated by the baseband signals. A detailed block diagram of
the AD9957 is shown in Figure 25.
The inverse sinc filter is available in all three modes.
06384-
005
PDCLK
I/Q IN
E
X
T
_P
W
R_DW
N
DAC_RSET
IOUT
TxENABLE
FTW
PW
DAC GAIN
θ
IN
VER
SE
S
INC
FILTE
R
CLOCK
FTW
PW
8
SYSCLK
PLL
÷2
CL
O
CK
M
O
DE
REF_CLK
REFCLK_OUT
XTAL_SEL
PARALLEL DATA
TIMING AND CONTROL
AD9957
ω
cos (ωt+θ)
sin (ωt+θ)
S
Y
NC_O
UT
S
Y
NC_I
N
P
LL_
LOC
K
P
LL_
LOOP
_
FILTE
R
MA
ST
ER
_
R
ESET
2
CCI
_O
V
F
L
O
SK
DDS
AUX
DAC
8-BIT
POWER
DOWN
CONTROL
RT
RAM
P
R
OFILE
SERIAL I/O
PORT
I/
O
_UP
DAT
E
PROGRAMMING
REGISTERS
3
I Q
IS QS
18
DAT
A
AS
S
E
M
BL
E
R
AND
F
O
RM
AT
T
E
R
I
Q
IS
QS
BL
ACKF
IN
I
NT
E
RF
ACE
18
16
HAL
F
-BAND
FILTE
R
S
(
4
×
)
IN
VER
SE
CCI
(1×
T
O
63×
)
HAL
F
-BAND
FILTE
R
S
(
4
×
)
IN
VER
SE
CCI
(1×
T
O
63×
)
OSK
INTERNAL CLOCK TIMING AND CONTROL
DAC
14-BIT
OUTPUT
SCALE
FACTOR
S
DI
O
CS
I/
O
_
R
ESET
S
CL
K
S
DO
Figure 25. Detailed Block Diagram
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