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| 型号： | AD9984AKSTZ-170 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 9/44页 |
| 文件大小： | 0K |
| 描述： | IC DISPLAY 10BIT 170MSPS 80LQFP |
| 标准包装： | 1 |
| 类型： | 接口 |
| 应用： | 显示器，处理，电视 |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 80-LQFP |
| 供应商设备封装： | 80-LQFP（14x14） |
| 包装： | 托盘 |
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AD9984A
Rev. 0 | Page 17 of 44
Sync Slicer
The purpose of the sync slicer is to extract the sync signal from
the green graphics or luminance video signal that is connected
to the SOG input. The sync signal is extracted in a two step
process. First, the SOG input is clamped to its negative peak,
(typically 0.3 V below the black level). Next, the signal goes to a
comparator with a variable trigger level (set by Register 0x1D,
Bits[7:3]), but nominally 0.128 V above the clamped level. The
sync slicer output is a digital composite sync signal containing
both Hsync and Vsync information (see Figure 10).
Sync Separator
As part of sync processing, the sync separator’s task is to extract
Vsync from the composite sync signal. It works on the idea that
the Vsync signal stays active for a much longer time than the
Hsync signal. By using a digital low-pass filter and a digital
comparator, the sync separator rejects pulses with small
durations (such as Hsyncs and equalization pulses) and only
passes pulses with large durations, such as Vsync (see Figure 10).
The threshold of the digital comparator is programmable
for maximum flexibility. To program the threshold duration,
write a value (N) to Register 0x11. The resulting pulse width
is N × 200 ns. If, for example, N = 5, the digital comparator
threshold is 1 μs. Any pulse less than 1 μs is rejected, while any
pulse greater than 1 μs passes through.
There are two factors to keep in mind when using the sync
separator. First, the resulting clean Vsync output is delayed
from the original Vsync by a duration equal to the digital
comparator threshold (N × 200 ns). Second, there is some
variability to the 200 ns multiplier value. The maximum
variability over all operating conditions is ±20% (160 ns to
240 ns). Because normal Vsync and Hsync pulse widths differ
by a factor of approximately 500 or more, the 20% variability is
not an issue.
Hsync Filter and Regenerator
The Hsync filter is used to eliminate any extraneous pulses from
the Hsync or SOG inputs, outputting a clean, low jitter signal
that is appropriate for mode detection and clock generation.
The Hsync regenerator is used to recreate a clean, but not low
jitter, Hsync signal that can be used for mode detection and
counting Hsyncs per Vsync. The Hsync regenerator has a high
degree of tolerance to extraneous and missing pulses on the
Hsync input, but is not appropriate for use by the PLL in
creating the pixel clock due to jitter.
The Hsync regenerator runs automatically and requires no setup
to operate. The Hsync filter requires the setting up of a filter
window. The filter window sets a periodic window of time
around the regenerated Hsync leading edge where valid Hsyncs
are allowed to occur. The general idea is that extraneous pulses
on the sync input occur outside of this filter window and are
thus, filtered out. To set the filter window timing, program a
value (x) into Register 0x23. The resulting filter window time is
±x times 25 ns around the regenerated Hsync leading edge. Just
as for the sync separator threshold multiplier, allow a ±20%
variance in the 25 ns multiplier to account for all operating
conditions (20 ns to 30 ns range).
A second output from the Hsync filter is a status bit (Register 0x25,
Bit 1) that indicates if extraneous pulses are present on the
incoming sync signal. Extraneous pulses are often included for
copy protection purposes, so this status bit can be used to detect
such pulses.
The filtered Hsync (rather than the raw HSYNCx/SOGINx
signal) for pixel clock generation by the PLL is controlled by
Register 0x20, Bit 2. The regenerated Hsync (rather than
the raw HSYNCx/SOGINx signal) for the sync processing is
controlled by Register 0x20, Bit 1. Using the filtered Hsync
and regenerated Hsync is recommended. See Figure 11 for an
illustration of a filtered Hsync.
SOG INPUT
SOGOUT OUTPUT
CONNECTED TO
HSYNCIN
NEGATIVE PULSE WIDTH = 40 SAMPLE CLOCKS
COMPOSITE
SYNC
AT HSYNCIN
VSYNCOUT
FROM SYNC
SEPARATOR
–300mV
+300mV
700mV MAXIMUM
0mV
06
47
6-
0
09
Figure 10. Sync Slicer and Sync Separator Output
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相关代理商/技术参数 |
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|---|---|
| AD9984APCBZ | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance 10-Bit Display Interface |
| AD9984KSTZ-110 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9984KSTZ-140 | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD9984KSTZ-170 | 制造商:Analog Devices 功能描述: |
| AD9985 | 制造商:AD 制造商全称:Analog Devices 功能描述:110 MSPS/140 MSPS Analog Interface for Flat Panel Displays |
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