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参数资料
型号： ADAU1381BCBZ-RL
厂商： Analog Devices Inc
文件页数： 26/84页
文件大小： 0K
描述： IC AUDIO CODEC STEREO LN 30WLCSP
标准包装： 5,000
类型： 立体声音频
数据接口： 串行，SPI?
分辨率（位）： 24 b
ADC / DAC 数量： 2 / 2
三角积分调变： 无
S/N 比，标准 ADC / DAC (db)： 97 / 100
动态范围，标准 ADC / DAC (db)： 96.5 / 100
电压 - 电源，模拟： 1.8 V ~ 3.65 V
电压 - 电源，数字： 1.63 V ~ 3.65 V
工作温度： -25°C ~ 85°C
安装类型： 表面贴装
封装/外壳： 30-UFBGA，WLCSP
供应商设备封装： 30-WLCSP（3.4x2.64）
包装： 带卷 (TR)
配用： EVAL-ADAU1381Z-ND - BOARD EVALUATION FOR ADAU1381
ADAU1381
Rev. B | Page 32 of 84
PLAYBACK SIGNAL PATH
SPP
AOUTL
LEFT PLAYBACK
MIXER
LEFT
DAC
LINE OUT
AMPLIFIER
AOUTR
RIGHT
DAC
LINE OUT
AMPLIFIER
RIGHT PLAYBACK
MIXER
MONO
PLAYBACK
MIXER
MONO
OUTPUT
GAIN
MONO
PLAYBACK
BEEP GAIN
BEEP FROM
RECORD PGA
SPN
LEFT
PLAYBACK
BEEP GAIN
RIGHT
PLAYBACK
BEEP GAIN
–1
MONO OUTPUT
INVERTER
08
31
3-
03
3
Figure 35. Playback Signal Path Diagram
OUTPUT SIGNAL PATHS
The outputs of the ADAU1381 include a left and right line output
and speaker driver. The beep input signal can be mixed into any
of these outputs, with separate gain control for each path.
DIGITAL-TO-ANALOG CONVERTERS
The ADAU1381 uses two 24-bit Σ-Δ digital-to-analog converters
(DACs) with selectable oversampling rates of 64× or 128×. The
full-scale output of the DACs depends on AVDD1. At 3.3 V, the
full-scale output level is 1.0 V rms.
Digital DAC Volume Control
The DAC output (digital output) volume can be adjusted in
Register 16427 (0x402B), left DAC attenuator, for the left channel
digital volume control and in Register 16428 (0x402C), right
DAC attenuator, for the right channel digital volume control.
De-Emphasis Filter
A de-emphasis filter is used in the DAC path to remove high
frequency noise in an FM system. This filter can be enabled or
disabled in Register 16426 (0x402A), DAC control.
LINE OUTPUTS
The AOUTL and AOUTR pins are the left and right line outputs,
respectively. Both outputs have a line output amplifier that can
be set in the control registers.
The left playback mixer is dedicated to the AOUTL output. This
mixer mixes the left DAC and the beep signal.
Similarly, the right playback mixer mixes the right DAC and the
beep input and is dedicated to the AOUTR output.
SPEAKER OUTPUT
The SPP and SPN pins are the positive and negative speaker
outputs, respectively. Each output has a speaker driver.
The speaker outputs are derived from the mono playback mixer,
which sums the right and left DAC outputs and mixes with the
beep signal. The mixer can be controlled in Register 16415
(0x401F), playback mono mixer control.
The drivers are low noise, Class AB mono amplifiers designed to
drive 8 Ω, 400 mW speakers. The output is differential and does
not require external capacitors. The gain settings for the speaker
drivers can be set in Register 16423 (0x4027), playback speaker
output control. In this register, the drivers can be set for any of
the four gain settings: 0 dB, 2 dB, 4 dB, or 6 dB. Additionally,
the speaker driver can be muted or powered down completely.
For pop and click suppression, an internal precharge sequence with
output gating/enabling occurs after the mono driver is enabled.
The sequence lasts for 8 ms, and then the internal mute signal
rising edge occurs (see Figure 36 for the power-up sequence
timing diagram).
The power-down sequence is essentially the reverse of the start-
up sequence, as depicted in Figure 37.
SPEAKER
OUTPUT
ENABLE
MONO
OUTPUT
MUTE
SPP
SPN
HIGH-Z
VCM
IAVDD2
<1A
1.1mA
2.3mA
2.3mA + SIGNAL
CURRENT
DAC
BEEP
DAC VOLUME MUTED
BEEP VOLUME MUTED
DAC VOLUME
INCREASES
BEEP VOLUME
INCREASES
4ms
0
8313-
034
Figure 36. Speaker Driver Power-Up Sequence
SPEAKER
OUTPUT
ENABLE
MONO
OUTPUT
MUTE
SPP
SPN
IAVDD2
DAC
BEEP
HIGH-Z
VCM
<1A
1.1mA
2.3mA
2.3mA + SIGNAL
CURRENT
DAC VOLUME MUTED
BEEP VOLUME MUTED
DAC VOLUME
DECREASES
BEEP VOLUME
DECREASES
4ms
0
8313
-035
Figure 37. Speaker Driver Power-Down Sequence
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