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参数资料
| 型号： | ADAV801ASTZ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 消费家电 |
| 英文描述： | Audio Codec for Recordable DVD |
| 中文描述： | SPECIALTY CONSUMER CIRCUIT, PDSO64 |
| 封装： | ROHS COMPLIANT, MS-026BCD, LQFP-64 |
| 文件页数： | 22/56页 |
| 文件大小： | 1405K |
| 代理商： | ADAV801ASTZ |
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ADAV801
PLL SECTION
The ADAV801 features a dual PLL configuration to generate
independent system clocks for asynchronous operation.
Figure 37 shows the block diagram of the PLL section. The PLL
generates the internal and system clocks from a 27 MHz clock.
This clock is generated either by a crystal connected between
XIN and XOUT, as shown in Figure 35, or from
clock source connected directly to XIN. A 54 MHz clock can
also be used, if the internal clock divider is used.
Rev. 0 | Page 22 of 56
an external
C
C
XTA
0
L
X
X
Figure 35. Crystal Connection
Both PLLs (PLL1 and PLL2) can be programmed independently
and can accommodate a range of sampling rates (32/44.1/48
kHz) with selectable system clock oversampling rates of 256 and
384. Higher oversampling rates can also be selected by enabling
the doubling of the sampling rate to give 512 or 768 × f
S
ratios.
Note that this option also allows oversampling ratios of 256 or
384 at double sample r
ates of 64/88.2/96 kH
z.
The PLL outputs can be routed internally to act as clock sources
for the oth
on. The outputs of the PLLs are also available on the three
SYSCLK pins. Figure 38 shows how the PLLs can be configured
to provide the sampling clocks.
, and so
MCLK Selection
er component blocks such as the ADC, DAC
Table 7. PLL Frequency Selection Options
PLL
1
2A
2B
Sample Rate (f
S
)
32/44.1/48 kHz
64/88.2/96 kHz
32/44.1/48 kHz
64/88.2/96 kHz
Same as f
S
selected
For PLL 2A
Normal f
S
256/384 × f
S
256/384 × f
S
512 × f
S
512 × f
S
Double f
S
512/768 × f
S
256/384 × f
S
512/768 × f
S
256/384 × f
S
The PLLs require some external components to operate
correctly. These c
omponents, shown in Figure 3
filter that integrates the current pulses from a charge pum
produces a voltage that is used to tune the VCO. Good quali
capacitors, such as PPS film, are recommended. Figure 37 sh
a block diagram of the PLL section, including master clock
selection. Figure 38 shows how the clock frequencies at the
clock output pins, SYSCLK1 to SYSCLK 3, and the internal PLL
clock values, PLL1 and PLL2, are selected.
6, form a loop
p and
ty
ows
d as master clocks
e DAC or ADC.
pins, which should be
se from being
cal noi
g onto the loop filter pi
r t
e ADAV801
nd gro
t electri
ouplin
nv
ns.
The clock nodes, PLL1 and PLL2, can be use
fo he other blocks in th
Th PLL has separate supply a
as c ean as possible to preven
co
erted into clock jitter by c
such as th
und
0
PLL BLOCK
3.3k
PLL_LFx
100nF
AVDD
6.8nF
Figure 36. PLL Loop Filter
0
MCLKI
REG 0x
BIT
MCLKO
REG 0x74
BIT 5
G 0x74
BIT 4
REG 0x78
BIT 6
78
7
PHASE
DETECTOR
AND LOOP
FILTER
PLL1
SYSCLK1
SYSCLK2
SYSCLK3
PLL_LF2
XOUT
RE
XIN
PLL_LF1
÷
2
÷
2
VCO
÷
N
OUTPUT
SCALER N1
PHASE
DETECTOR
AND LOOP
FILTER
PLL2
VCO
÷
N
OUTPUT
SCALER N2
OUTPUT
SCALER N3
Section Block Diagram
Figure 37. PLL
相关PDF资料 |
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| ADAV801ASTZ-REEL | Audio Codec for Recordable DVD |
| ADC0800PCD | ADC0800 8-Bit A/D Converter |
| ADC0800PD | ADC0800 8-Bit A/D Converter |
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADAV801ASTZ-REEL | 功能描述:IC CODEC AUDIO R-DVD 3.3V 64LQFP RoHS:是 类别:集成电路 (IC) >> 接口 - 编解码器 系列:- 标准包装:2,500 系列:- 类型:立体声音频 数据接口:串行 分辨率（位）:18 b ADC / DAC 数量:2 / 2 三角积分调变:是 S/N 比，标准 ADC / DAC (db):81.5 / 88 动态范围，标准 ADC / DAC (db):82 / 87.5 电压 - 电源，模拟:2.6 V ~ 3.3 V 电压 - 电源，数字:1.7 V ~ 3.3 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:48-WFQFN 裸露焊盘 供应商设备封装:48-TQFN-EP（7x7） 包装:带卷 (TR) |
| ADAV802AST | 制造商:Analog Devices 功能描述:AUDIO CODEC FOR RECORDABLE DVD - Bulk |
| ADAV802ASTZ | 制造商:Analog Devices 功能描述: |
| ADAV803 | 制造商:AD 制造商全称:Analog Devices 功能描述:Audio Codec for Recordable DVD |
| ADAV803AST | 制造商:Analog Devices 功能描述:AUDIO CODEC FOR RECORDABLE DVD - Bulk |
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