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参数资料
| 型号： | ADC0811CCV |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 8-Bit Serial I/O A/D Converter With 11-Channel Multiplexer |
| 中文描述： | 11-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20 |
| 封装： | PLASTIC, LCC-20 |
| 文件页数： | 3/14页 |
| 文件大小： | 323K |
| 代理商： | ADC0811CCV |
Electrical Characteristics
The following specifications apply for V
CC
e
4.75V to 5.25V, V
REF
e a
4.6V to (V
CC
a
0.1V),
w
2 CLK
e
2.097 MHz unless
otherwise specified.
Boldface limits apply from T
MIN
to T
MAX
;
all other limits T
A
e
T
J
e
25
§
C. (Continued)
Parameter
Conditions
ADC0811CCJ
ADC0811BCN, ADC0811BCV
ADC0811CCN, ADC0811CCV
Units
Typical
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Typical
(Note 6)
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
DIGITAL AND DC CHARACTERISTICS
V
IN(1)
, Logical ‘‘1’’ Input
Voltage (Min)
V
CC
e
5.25V
2.0
2.0
2.0
V
V
IN(0)
, Logical ‘‘0’’ Input
Voltage (Max)
V
CC
e
4.75V
0.8
0.8
0.8
V
I
IN(1)
, Logical ‘‘1’’ Input
Current (Max)
V
IN
e
5.0V
0.005
2.5
0.005
2.5
2.5
m
A
I
IN(0)
, Logical ‘‘0’’ Input
Current (Max)
V
IN
e
0V
b
0.005
b
2.5
b
0.005
2.5
b
2.5
m
A
V
OUT(1)
, Logical ‘‘1’’
Output Voltage (Min)
V
CC
e
4.75V
I
OUT
eb
360
m
A
I
OUT
eb
10
m
A
V
CC
e
5.25V
I
OUT
e
1.6 mA
V
OUT
e
0V
V
OUT
e
5V
V
OUT
e
0V
2.4
4.5
2.4
4.5
2.4
4.5
V
V
V
OUT(0)
, Logical ‘‘0’’
Output Voltage (Max)
0.4
0.4
0.4
V
I
OUT
, TRI-STATE Output
Current (Max)
b
0.01
0.01
b
3
3
b
0.01
0.01
b
3
3
b
3
3
m
A
m
A
I
SOURCE
, Output Source
Current (Min)
b
12
b
6.5
b
14
b
6.5
b
6.5
mA
I
SINK
, Output Sink Current (Min)
I
CC
, Supply Current (Max)
I
REF
(Max)
V
OUT
e
V
CC
CS
e
1, V
REF
Open
V
REF
e
5V
18
8.0
16
8.0
8.0
mA
1
2.5
1
2.5
2.5
mA
0.7
1
0.7
1
1
mA
AC CHARACTERISTICS
Tested
Limit
(Note 7)
Design
Limit
(Note 8)
Parameter
Conditions
Typical
(Note 6)
Units
w
2 CLK
,
w
2
Clock Frequency
MIN
0.70
1.0
MHz
MAX
3.0
2.0
2.1
S
CLK
, Serial Data Clock
Frequency
MIN
5.0
KHz
MAX
700
525
525
T
C
, Conversion Process Time
MIN
Not Including MUX
Addressing and
Analog Input
Sampling Times
48
48
w
2
cycles
MAX
64
64
t
ACC
, Access Time Delay From CS
Falling Edge to DO Data Valid
MIN
1
w
2
cycles
MAX
3
t
SET-UP
, Minimum Set-up Time of CS Falling
Edge to S
CLK
Rising Edge
t
HCS
, CS Hold Time After the Falling
Edge of S
CLK
t
CS
, Total CS Low Time
4/
w
2CLK
a
1
2 S
CLK
sec
0
ns
MIN
t
set-up
a
8/S
CLK
sec
MAX
t
CS
(min)
a
48/
w
2CLK
sec
t
HDI
, Minimum DI Hold Time from
S
CLK
Rising Edge
t
HDO
, Minimum DO Hold Time from S
CLK
Falling Edge
0
0
ns
R
L
e
30k,
C
L
e
100 pF
10
ns
3
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