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参数资料
| 型号： | ADC0811CCV |
| 厂商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分类： | ADC |
| 英文描述： | 8-Bit Serial I/O A/D Converter With 11-Channel Multiplexer |
| 中文描述： | 11-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PQCC20 |
| 封装： | PLASTIC, LCC-20 |
| 文件页数： | 7/14页 |
| 文件大小： | 323K |
| 代理商： | ADC0811CCV |
Timing Diagrams
(Continued)
CS High During Conversion
TL/H/5587–4
CS Low During Conversion
TL/H/5587–5
Note:
DO and DI lines share the 8-bit I/O shift register(see Functional Block Diagram). Since the MUX address bits are shifted in on S
CLK
rising edges while S
CLK
falling edges shift out conversion data on DO, the eighth falling edge of S
CLK
will shift out the MSB MUX address bit (A7) on DO. Thus, if addressing channels
CH8–CH10, a high DO will occur momentarily (one
w
2
clock period) until the 8-bit I/O shift register is cleared by the internal EOC signal.
Channel Addressing Table
TABLE I. ADC 0811 Channel Addressing
MUX ADDRESS
ANALOG CHANNEL
SELECTED
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
0
0
0
0
0
0
0
1
0
0
1
0
0
0
1
1
0
1
0
0
0
1
0
1
0
1
1
0
0
1
1
1
1
0
0
0
1
0
0
1
1
0
1
0
1
0
1
1
1
1
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
CH0
CH1
CH2
CH3
CH4
CH5
CH6
CH7
CH8
CH9
CH10
V
TEST
LOGIC TEST MODE
*
*
Analog channel inputs CH0 thru CH3 are logic outputs
7
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