参数资料
型号: ADC0833CCN
厂商: NATIONAL SEMICONDUCTOR CORP
元件分类: ADC
英文描述: 8-Bit Serial I/O A/D Converter with 4-Channel Multiplexer
中文描述: 4-CH 8-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDIP14
封装: 0.300 INCH, PLASTIC, DIP-14
文件页数: 9/20页
文件大小: 316K
代理商: ADC0833CCN
Timing Diagram
TL/H/5607–5
Functional Description
1.0 MULTIPLEXER ADDRESSING
The design of the ADC0833 utilizes a sample-data compar-
ator structure which provides for a differential analog input
to be converted by a successive approximation routine.
The actual voltage converted is always the difference be-
tween an assigned ‘‘
a
’’ input terminal and a ‘‘
b
’’ input ter-
minal. The polarity of each input terminal of the pair being
converted indicates which line the converter expects to be
the most positive. If the assigned ‘‘
a
’’ input is less than the
‘‘
b
’’ input the converter responds with an all zeros output
code.
A unique input multiplexing scheme has been utilized to pro-
vide multiple analog channels with software-configurable
single-ended (ground referred) or differential inputs. The an-
alog signal conditioning required in transducer-based data
acquisition systems is significantly simplified with this type
of input flexibility. One converter package can now handle
ground referenced inputs and true differential inputs.
A particular input configuration is assigned during the MUX
addressing sequence, prior to the start of a conversion. The
MUX address selects which of the analog inputs are to be
enabled and whether this input is single-ended or differen-
tial. In the differential case, it also assigns the polarity of the
channels. Differential inputs are restricted to adjacent chan-
nel pairs. For example channel 0 and channel 1 may be
selected as a differential pair. Channel 0 or 1 cannot act
differentially with any other channel. In addition to selecting
differential mode the sign may also be selected. Channel 0
may be selected as the positive input and channel 1 as the
negative input or vice versa. This programmability is best
illustrated by the MUX addressing codes shown in the fol-
lowing table. The MUX address is shifted into the converter
through the DI line.
TABLE I. MUX Addressing
Single-Ended MUX Mode
Address
Channel
Y
SGL/
ODD/
SELECT
0
1
2
3
DIF
SIGN
1
0
1
0
0
1
a
1
0
1
1
a
1
1
0
1
a
1
1
1
1
a
COM is internally ties to a GND
Differential MUX Mode
Address
Channel
Y
SGL/
ODD/
SELECT
0
1
2
3
DIF
SIGN
1
0
0
0
0
1
a
b
0
0
1
1
a
b
0
1
0
1
b
a
0
1
1
1
b
a
9
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相关代理商/技术参数
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