参数资料
型号: ADCLK854BCPZ
厂商: Analog Devices Inc
文件页数: 5/16页
文件大小: 0K
描述: IC CLOCK BUFFER MUX 2:12 48LFCSP
设计资源: Clock Distribution Circuit with Pin-Programmable Output Frequency, Output Logic Levels, and Fanout (CN0152)
标准包装: 1
类型: 扇出缓冲器(分配),多路复用器
电路数: 1
比率 - 输入:输出: 2:12
差分 - 输入:输出: 是/是
输入: CML,CMOS,HSTL,LVDS,LVPECL
输出: CMOS,LVDS
频率 - 最大: 1.2GHz
电源电压: 1.71 V ~ 1.89 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 48-VFQFN 裸露焊盘,CSP
供应商设备封装: 48-LFCSP
包装: 托盘
ADCLK854
Rev. 0 | Page 13 of 16
CONTROL AND FUNCTION PINS
CTRL_A—Logic Select
This pin selects either CMOS (high) or LVDS (low) logic for
Output 3, Output 2, Output 1, and Output 0. This pin has an
internal 200 kΩ pull-down resistor.
CTRL_B—Logic Select
This pin selects either CMOS (high) or LVDS (low) logic for
Output 7, Output 6, Output 5, and Output 4. This pin has an
internal 200 kΩ pull-down resistor.
CTRL_C—Logic Select
This pin selects either CMOS (high) or LVDS (low) logic for
Output 11, Output 10, Output 9, and Output 8. This pin has an
internal 200 kΩ pull-down resistor.
IN_SEL—Clock Input Select
A logic low selects CLK0 and CLK0 whereas a logic high selects
CLK1 and CLK1. This pin has an internal 200 kΩ pull-down
resistor.
Sleep Mode
Sleep mode powers down the chip except for the internal band
gap. The input is active high, which puts the outputs into a
high-Z state. This pin has a 200 kΩ pull-down resistor.
POWER SUPPLY
The ADCLK854 requires a 1.8 V ± 5% power supply for VS. Best
practice recommends bypassing the power supply on the PCB
with adequate capacitance (>10 μF), and bypassing all power
pins with adequate capacitance (0.1 μF) as close to the part as
possible. The layout of the ADCLK854 evaluation board
(ADCLK854/PCBZ) provides a good layout example.
Exposed Metal Paddle
The exposed metal paddle on the ADCLK854 package is an
electrical connection as well as a thermal enhancement. For the
device to function properly, the paddle must be properly
attached to ground (GND). The ADCLK854 dissipates heat
through its exposed paddle. The PCB acts as a heat sink for the
ADCLK854. The PCB attachment must provide a good thermal
path to a larger heat dissipation area, such as the ground plane
on the PCB. This requires a grid of vias from the top layer down
to the ground plane. See Figure 23 for an example.
VIAS TO GND PLANE
07
21
8-
023
Figure 23. PCB Land for Attaching Exposed Paddle
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ADCLK905BCPZ-R7 功能描述:IC CLK/DATA BUFF DVR 1:1 16LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟缓冲器,驱动器 系列:SIGe 产品培训模块:High Bandwidth Product Overview 标准包装:1,000 系列:Precision Edge® 类型:扇出缓冲器(分配) 电路数:1 比率 - 输入:输出:1:4 差分 - 输入:输出:是/是 输入:CML,LVDS,LVPECL 输出:CML 频率 - 最大:2.5GHz 电源电压:2.375 V ~ 2.625 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘,16-MLF? 供应商设备封装:16-MLF?(3x3) 包装:带卷 (TR)