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| 型号： | ADCMP605BCPZ-WP |
| 厂商： | Analog Devices Inc |
| 文件页数： | 12/16页 |
| 文件大小： | 0K |
| 描述： | IC COMP TTL/CMOS 1CHAN 12LFCSP |
| 标准包装： | 50 |
| 类型： | 带锁销 |
| 元件数： | 1 |
| 输出类型： | 补充型，LVDS，满摆幅 |
| 电压 - 电源，单路/双路(±)： | 2.5 V ~ 5.5 V |
| 电压 - 输入偏移（最小值）： | 5mV @ 3V |
| 电流 - 输入偏压（最小值）： | 5µA @ 3V |
| 电流 - 输出（标准）： | 50mA |
| 电流 - 静态（最大值）： | 3mA |
| CMRR, PSRR（标准）： | 50dB CMRR，50dB PSRR |
| 传输延迟（最大）： | 3ns |
| 磁滞： | 100µV |
| 工作温度： | -40°C ~ 125°C |
| 封装/外壳： | 12-VFQFN 裸露焊盘，CSP |
| 安装类型： | 表面贴装 |
| 包装： | 托盘 - 晶粒 |
ADCMP604/ADCMP605
Rev. A | Page 5 of 16
TIMING INFORMATION
Figure 2 illustrates the ADCMP604/ADCMP605 latch timing relationships. Table 2 provides definitions of the terms shown in Figure 2.
1.1V
50%
VN ± VOS
DIFFERENTIAL
INPUT VOLTAGE
LATCH ENABLE
Q OUTPUT
tH
tPDL
tPLOH
tF
VIN
VOD
tS
tPL
50%
Q OUTPUT
tPDH
tPLOL
tR
05
91
6-
02
5
Figure 2. System Timing Diagram
Table 2. Timing Descriptions
Symbol
Timing
Description
tPDH
Input-to-Output High Delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output low-to-high transition.
tPDL
Input-to-Output Low Delay
Propagation delay measured from the time the input signal crosses the reference (± the
input offset voltage) to the 50% point of an output high-to-low transition.
tPLOH
Latch Enable-to-Output High Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output low-to-high transition.
tPLOL
Latch Enable-to-Output Low Delay
Propagation delay measured from the 50% point of the latch enable signal low-to-high
transition to the 50% point of an output high-to-low transition.
tH
Minimum Hold Time
Minimum time after the negative transition of the latch enable signal that the input
signal must remain unchanged to be acquired and held at the outputs.
tPL
Minimum Latch Enable Pulse Width
Minimum time that the latch enable signal must be high to acquire an input signal change.
tS
Minimum Setup Time
Minimum time before the negative transition of the latch enable signal occurs that an
input signal change must be present to be acquired and held at the outputs.
tR
Output Rise Time
Amount of time required to transition from a low to a high output as measured at the
20% and 80% points.
tF
Output Fall Time
Amount of time required to transition from a high to a low output as measured at the
20% and 80% points.
VOD
Voltage Overdrive
Difference between the input voltages, VA and VB.
B
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADCMP605BCPZ-WP1 | 制造商:AD 制造商全称:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply LVDS Comparators |
| ADCMP606 | 制造商:AD 制造商全称:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators |
| ADCMP606_0610 | 制造商:AD 制造商全称:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators |
| ADCMP606_07 | 制造商:AD 制造商全称:Analog Devices 功能描述:Rail-to-Rail, Very Fast, 2.5 V to 5.5 V, Single-Supply CML Comparators |
| ADCMP606BKSZ-R2 | 功能描述:IC COMP TTL/CMOS 1CHAN SC70-6 RoHS:是 类别:集成电路 (IC) >> 线性 - 比较器 系列:- 产品培训模块:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 标准包装:50 系列:- 类型:带电压基准 元件数:4 输出类型:开路漏极 电压 - 电源，单路/双路(±):2.5 V ~ 11 V，±1.25 V ~ 5.5 V 电压 - 输入偏移（最小值）:10mV @ 5V 电流 - 输入偏压（最小值）:- 电流 - 输出（标准）:0.015mA @ 5V 电流 - 静态（最大值）:8.5µA CMRR, PSRR（标准）:80dB CMRR，80dB PSRR 传输延迟（最大）:- 磁滞:- 工作温度:0°C ~ 70°C 封装/外壳:16-SOIC（0.154"，3.90mm 宽） 安装类型:表面贴装 包装:管件 产品目录页面:1386 (CN2011-ZH PDF) |
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