参数资料
型号: ADE7166ASTZF8-RL
厂商: Analog Devices Inc
文件页数: 117/152页
文件大小: 0K
描述: IC ENERGY METER 1PHASE 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1,500
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Table 116. Timer 0 High Byte SFR (TH0, Address 0x8C)
Mode 0 (13-Bit Timer/Counter)
Bit
[7:0]
Mnemonic
TH0
Default
0
Description
Timer 0 data high byte.
Mode 0 configures an 8-bit timer/counter. Figure 97 shows
Mode 0 operation. Note that the divide-by-12 prescaler is not
Table 117. Timer 0 Low Byte SFR (TL0, Address 0x8A)
Bit Mnemonic Default Description
present on the single-cycle core.
f CORE
[7:0]
TL0
0
Timer 0 data low byte.
C/T0 = 0
TL0 TH0
(5 BITS) (8 BITS)
TF0
INTERRUPT
Table 118. Timer 1 High Byte SFR (TH1, Address 0x8D)
C/T0 = 1
Bit
Mnemonic
Default
Description
P0.6/T0
[7:0]
TH1
0
Timer 1 data high byte.
TR0
CONTROL
Table 119. Timer 1 Low Byte SFR (TL1, Address 0x8B)
Bit Mnemonic Default Description
GATE
I NT0
[7:0]
TL1
0
Timer 1 data low byte.
Figure 97. Timer/Counter 0, Mode 0
Table 120. Timer 2 High Byte SFR (TH2, Address 0xCD)
In this mode, the timer register is configured as a 13-bit register.
Bit
[7:0]
Mnemonic
TH2
Default
0
Description
Timer 2 data high byte.
As the count rolls over from all 1s to all 0s, it sets the timer
overflow flag, TF0 (Address 0x88[5]). TF0 can then be used to
request an interrupt. The counted input is enabled to the timer
Table 121. Timer 2 Low Byte SFR (TL2, Address 0xCC)
when TR0 = 1 and either Gate0 to 0 or INT0 = 1. Setting Gate0
Bit
[7:0]
Mnemonic
TL2
Default
0
Description
Timer 2 data low byte.
to 1 allows the timer to be controlled by the external input INT0
to facilitate pulse width measurements. TR0 is a control bit in
Table 122. Timer 2 Reload/Capture High Byte SFR
(RCAP2H, Address 0xCB)
Bit Mnemonic Default Description
[7:0] TH2 0 Timer 2 reload/
capture high byte.
Table 123. Timer 2 Reload/Capture Low Byte SFR (RCAP2L,
Address 0xCA)
the Timer/Counter 0 and Timer/Counter 1 control SFR
(TCON, Address 0x88); the Gate0/Gate1 bits are in
Timer/Counter 0 and Timer/Counter 1 mode SFR (TMOD,
Address 0x89). The 13-bit register consists of all eight bits of
Timer 0 high byte SFR (TH0, Address 0x8C) and the lower five
bits of Timer 0 low byte SFR (TL0, Address 0x8A). The upper
three bits of TL0 SFR are indeterminate and should be ignored.
Setting the run flag (TR0) does not clear the registers.
Bit
[7:0]
Mnemonic
TL2
Default
0
Description
Timer 2 reload/
capture low byte.
Mode 1 (16-Bit Timer/Counter)
Mode 1 is the same as Mode 0 except that the Mode 1 timer
register runs with all 16 bits. Mode 1 is shown in Figure 98.
TIMER 0 AND TIMER 1
f CORE
Timer 0 High/Low and Timer 1 High/Low Data SFRs
Each timer consists of two 8-bit SFRs. They are Timer 0 high
C/T0 = 0
C/T0 = 1
TL0 TH0
(8 BITS) (8 BITS)
TF0
INTERRUPT
byte (TH0, Address 0x8C), Timer 0 low byte (TL0, Address 0x8A),
P0.6/T0
Timer 1 high byte (TH1, Address 0x8D), and Timer 1 low byte
(TL1, Address 0x8B). These SFRs can be used as independent
registers or combined into a single 16-bit register, depending on
TR0
CONTROL
the timer mode configuration (see Table 116 to Table 119).
Timer/Counter 0 and Timer/Counter 1 Operating Modes
GATE
INT 0
Figure 98. Timer/Counter 0, Mode 1
This section describes the operating modes for Timer/Counter 0
and Timer/Counter 1. Unless otherwise noted, these modes of
operation are the same for both Timer 0 and Timer 1.
Rev. B | Page 117 of 152
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