参数资料
型号: ADE7166ASTZF8-RL
厂商: Analog Devices Inc
文件页数: 49/152页
文件大小: 0K
描述: IC ENERGY METER 1PHASE 64LQFP
产品变化通告: Product Discontinuance 27/Oct/2011
标准包装: 1,500
输入阻抗: *
测量误差: *
电压 - 高输入/输出: *
电压 - 低输入/输出: *
电流 - 电源: *
电源电压: *
测量仪表类型: *
工作温度: *
安装类型: 表面贴装
封装/外壳: 64-LQFP
供应商设备封装: 64-LQFP(10x10)
包装: 带卷 (TR)
ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/ADE7569
Table 45. Interrupt Enable 3 SFR (MIRQENH, Address 0xDB)
Bit
[7:6]
5
4
3
2
1
0
Interrupt Enable Bit
Reserved
WFSM
PKI
PKV
CYCEND
ZXTO
ZX
Description
Reserved.
When this bit is set to Logic 1, the WFSM flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the PKI flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the PKV flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the CYCEND flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the ZXTO flag set creates a pending ADE interrupt to the 8052 core.
When this bit is set to Logic 1, the ZX flag set creates a pending ADE interrupt to the 8052 core.
ANALOG INPUTS
Each ADE7116/ADE7156/ADE7166/ADE7169/ADE7566/
GAIN REGISTER*
CURRENT AND VOLTAGE CHANNELS PGA CONTROL
ADE7569 has two fully differential voltage input channels. The
7
6
5
4
3
2
1
0
maximum differential input voltage for the V P /V N and I P /I N
0
0
0
0
0
0
0
0
ADDR:
0x1B
input pairs is ±0.4 V.
For the ADE7116/ADE7156/ADE7166/ADE7169, PGA1 = 1 is not
recommended because, at full scale, when both I PA and I PB are
180° out of phase, the ADC can be overranged. It is recom-
PGA2 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
PGA1 GAIN SELECT
000 = × 1
001 = × 2
010 = × 4
011 = × 8
100 = × 16
mended, for these products, that PGA1 = 2, 4, 8, or 16 be used.
Each analog input channel has a programmable gain amplifier
(PGA) with possible gain selections of 1, 2, 4, 8, and 16. The
gain selections are made by writing to the GAIN register (see
CFSIGN_OPT
RESERVED
*REGISTER CONTENTS SHOW POWER-ON DEFAULTS.
Figure 41. Analog Gain Register
Table 38 and Figure 41). Bit 2 to Bit 0 select the gain for the PGA
in the current channel, and Bit 7 to Bit 5 select the gain for the
7
6
5
GAIN[7:0]
4 3 2
1
0
PGA in the voltage channel. Figure 42 shows how a gain selec-
0
0
0
0
0
0
0
0
tion for the current channel is made using the gain register.
GAIN (K)
SELECTION
I P
V IN
K × V IN
I N
Figure 42. PGA in Current Channel
Rev. B | Page 49 of 152
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