参数资料
| 型号： | ADE7518ASTZF8 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/128页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METER MCU 8K 64LQFP |
| 产品变化通告： | Product Discontinuance 27/Oct/2011 |
| 特色产品： | ADE7518: Single-phase Energy-Measurement IC |
| 标准包装： | 160 |
| 输入阻抗： | * |
| 测量误差： | * |
| 电压 - 高输入/输出： | * |
| 电压 - 低输入/输出： | * |
| 电流 - 电源： | * |
| 电源电压： | * |
| 测量仪表类型： | * |
| 工作温度： | * |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 产品目录页面： | 797 (CN2011-ZH PDF) |
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ADE7518
Pin No.
37
38
39
40
41
42
43
44
45
46
47
48
49, 50
51
52, 53
54
55
56
57
58
59
60
61
62
63
64
Mnemonic
P1.0/RxD
P0.7/SS/T1
P0.6/SCLK/T0
P0.5/MISO
P0.4/MOSI/SDATA
P0.3/CF2
P0.2/CF1/RTCCAL
SDEN/P2.3
BCTRL/INT1/P0.0
XTAL2
XTAL1
INT0
V P , V N
EA
I P , I N
AGND
FP26
RESET
REF IN/OUT
V BAT
V INTA
V DD
V SWOUT
V INTD
DGND
V DCIN
Description
General-Purpose Digital I/O Port 1.0 or Receiver Data Input (Asynchronous).
General-Purpose Digital I/O Port 0.7, Slave Select When SPI is in Slave Mode, or Timer 1 Input.
General-Purpose Digital I/O Port 0.6, Clock Output for I 2 C or SPI Port, or Timer 0 Input.
General-Purpose Digital I/O Port 0.5 or Data Input for SPI Port.
General-Purpose Digital I/O Port 0.4, Data Output for SPI Port, or I 2 C-Compatible Data Line.
General-Purpose Digital I/O Port 0.3 or Calibration Frequency Logic Output 2. The CF2 logic output gives
instantaneous active, reactive, I rms , or apparent power information.
General-Purpose Digital I/O Port 0.2, Calibration Frequency Logic Output 1, or RTC Calibration Frequency
Logic Output. The CF1 logic output gives instantaneous active, reactive, I rms , or apparent power information.
The RTCCAL logic output gives access to the calibrated RTC output.
Serial Download Mode Enable or Digital Output Port P2.3. This pin is used to enable serial download mode
through a resistor when pulled low on power-up or reset. On reset, this pin momentarily becomes an input
and the status of the pin is sampled. If there is no pull-down resistor in place, the pin momentarily goes high
and then user code is executed. If the pin is pulled down on reset, the embedded serial download/debug
kernel executes, and this pin remains low during the internal program execution. After reset, this pin can be
used as a digital output port pin (P2.3).
Digital Input for Battery Control, External Interrupt Input 1, or General-Purpose Digital I/O Port 0.0. This logic
input connects V DD or V BAT to V SWOUT internally when set to logic high or logic low, respectively. When left
open, the connection between V DD and V SWOUT or between V BAT and V SWOUT is selected internally.
A crystal can be connected across this pin and XTAL1 (see the XTAL1 pin description) to provide a clock
source for the ADE7518. The XTAL2 pin can drive one CMOS load when an external clock is supplied at XTAL1
or by the gate oscillator circuit. An internal 6 pF capacitor is connected to this pin.
An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can be
connected across XTAL1 and XTAL2 to provide a clock source for the ADE7518. The clock frequency for
specified operation is 32.768 kHz. An internal 6 pF capacitor is connected to this pin.
External Interrupt Input 0.
Analog Inputs for Voltage Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.
This pin is used as an input for emulation. When held high, this input enables the device to fetch code from
internal program memory locations. The ADE7518 does not support external code memory. This pin should
not be left floating.
Analog Inputs for Current Channel. These inputs are fully differential voltage inputs with a maximum
differential level of ±400 mV for specified operation. This channel also has an internal PGA.
This pin provides the ground reference for the analog circuitry.
LCD Segment Output 26.
Reset Input, Active Low.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value of
1.2 V ± 0.1% and a typical temperature coefficient of 50 ppm/°C maximum. This pin should be decoupled
with a 1 μF capacitor in parallel with a ceramic 100 nF capacitor.
Power Supply Input from the Battery with a 2.4 V to 2.7 V Range. This pin is connected internally to V DD when
the battery is selected as the power supply for the ADE7518.
This pin provides access to the on-chip 2.5 V analog LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
3.3 V Power Supply Input from the Regulator. This pin is connected internally to V DD when the regulator is
selected as the power supply for the ADE7518. This pin should be decoupled with a 10 μF capacitor in
parallel with a ceramic 100 nF capacitor.
3.3 V Power Supply Output. This pin provides the supply voltage for the LDOs and internal circuitry of the
ADE7518. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
This pin provides access to the on-chip 2.5 V digital LDO. No external active circuitry should be connected to
this pin. This pin should be decoupled with a 10 μF capacitor in parallel with a ceramic 100 nF capacitor.
This pin provides the ground reference for the digital circuitry.
Analog Input for DC Voltage Monitoring. The maximum input voltage on this pin is V SWOUT with respect to
AGND. This pin is used to monitor the preregulated dc voltage.
Rev. 0 | Page 16 of 128
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