参数资料
型号: ADE7755ARSZ
厂商: Analog Devices Inc
文件页数: 15/20页
文件大小: 0K
描述: IC ENERGY METERING 1PHASE 24SSOP
标准包装: 59
输入阻抗: 390 千欧
测量误差: 0.1%
电压 - 高输入/输出: 2.4V
电压 - 低输入/输出: 0.8V
电流 - 电源: 3mA
电源电压: 4.75 V ~ 5.25 V
测量仪表类型: 单相
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-SSOP(0.209",5.30mm 宽)
供应商设备封装: 24-SSOP
包装: 管件
配用: EVAL-ADE7755ZEB-ND - BOARD EVALUATION FOR AD7755
ADE7755
HPF and Offset Effects
Figure 29 shows the effect of offsets on the active power calculation.
An offset on Channel 1 and Channel 2 contributes a dc component
after multiplication. Because the dc component is extracted by
the LPF, it accumulates as active power. If not properly filtered, dc
offsets introduce error to the energy accumulation. This problem is
easily avoided by enabling the HPF (that is, the AC/DC pin is
set to logic high) in Channel 1. By removing the offset from at
least one channel, no error component can be generated at dc
by the multiplication. Error terms at cos(ωt) are removed by the
LPF and the digital-to-frequency conversion (see the Digital-to-
0.30
0.25
0.20
0.15
0.10
0.05
0
–0.05
Frequency Conversion section).
{ V cos( ωt ) + V OS } × { I cos( ωt ) + I OS } =
–0.10
40
45
50
55 60
FREQUENCY (Hz)
65
70
V × I
2
V × I
2
+ V OS × I OS + V OS × I cos( ω t ) + I OS × V cos( ω t ) +
× cos( 2 ω t )
Figure 31. Phase Error Between Channels (40 Hz to 70 Hz)
DIGITAL-TO-FREQUENCY CONVERSION
The digital output of the low-pass filter after multiplication
contains the active power information. However, because this
V OS × I OS
V×I
2
DC COMPONENT (INCLUDING ERROR TERM)
IS EXTRACTED BY THE LPF FOR ACTIVE
POWER CALCULATION
LPF is not an ideal brick-wall filter implementation, the output
signal also contains attenuated components at the line frequency
and its harmonics, that is, cos(hωt) where h = 1, 2, 3, and so on.
The magnitude response of the filter is given by
I OS × V
H ( f ) =
1
1 + ( f / 8.9 Hz )
(4)
0
ω
V OS × I
2 ω
For a line frequency of 50 Hz, the filter gives an attenuation
FREQUENCY (RAD/s)
Figure 29. Effect of Channel Offset on the Active Power Calculation
The HPF in Channel 1 has an associated phase response that is
compensated for on chip. The phase compensation is activated
when the HPF is enabled and is disabled when the HPF is not
activated. Figure 30 and Figure 31 show the phase error between
channels with the compensation network activated. The ADE7755
is phase compensated up to 1 kHz, as shown. This ensures correct
active harmonic power calculation even at low power factors.
0.30
0.25
0.20
0.15
0.10
0.05
0
–0.05
of the 2ω (100 Hz) component of approximately ?22 dB. The
dominating harmonic is at twice the line frequency, that is,
cos(2 ωt), which is due to the instantaneous power signal.
Figure 32 shows the instantaneous active power signal at the
output of the LPF, which still contains a significant amount of
instantaneous power information, that is, cos(2 ωt). This signal
is then passed to the digital-to-frequency converter where it is
integrated (accumulated) over time to produce an output frequency.
This accumulation of the signal suppresses or averages out any
non-dc components in the instantaneous active power signal. The
average value of a sinusoidal signal is 0. Therefore, the frequency
generated by the ADE7755 is proportional to the average active
power. Figure 32 shows the digital-to-frequency conversion for
steady load conditions, that is, constant voltage and current.
–0.10
0
100
200
300
400 500 600 700
800
900
1000
FREQUENCY (Hz)
Figure 30. Phase Error Between Channels (0 Hz to 1 kHz)
Rev. A | Page 15 of 20
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