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参数资料
| 型号： | ADE7759ARSZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/36页 |
| 文件大小： | 0K |
| 描述： | IC ENERGY METERING 1PHASE 20SSOP |
| 标准包装： | 66 |
| 输入阻抗： | 390 千欧 |
| 测量误差： | 0.1% |
| 电压 - 高输入/输出： | 2.4V |
| 电压 - 低输入/输出： | 0.8V |
| 电流 - 电源： | 3mA |
| 电源电压： | 4.75 V ~ 5.25 V |
| 测量仪表类型： | 单相 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-SSOP（0.209"，5.30mm 宽） |
| 供应商设备封装： | 20-SSOP |
| 包装： | 管件 |
| 产品目录页面： | 797 (CN2011-ZH PDF) |
| 配用： | EVAL-ADE7759EBZ-ND - BOARD EVALUATION FOR ADE7759 |
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ADE7759
Address
0Bh
Name
APGAIN
R/W No. of Bits
R/W 12
Default
0h
Description
Active Power Gain Adjust. This is a 12-bit register. The active power
calculation can be calibrated by writing to this register. The calibration
range is ± 50% of the nominal full-scale active power. The resolution of the
gain adjust is 0.0244%/LSB—see Channel 1 ADC Gain Adjust section.
0Ch
PHCAL
R/W 8
0h
Phase Calibration Register. The phase relationship between Channel 1
and Channel 2 can be adjusted by writing to this 8-bit register. The
valid content of this twos complement register is between 9Eh and
5Ch, which is a phase difference of –2.365 ∞ to +2.221 ∞ at 60 Hz in
0.0241 ∞ steps—see Phase Compensation section.
0Dh
APOS
R/W 16
0h
Active Power Offset Correction. This 16-bit register allows small off-
sets in the Active Power calculation to be removed—see Active Power
Calculation section.
0Eh
ZXTOUT
R/W 12
FFFh
Zero Cross Timeout. If no zero crossings are detected on Channel 2
within a time period specified by this 12-bit register, the interrupt
request line ( IRQ ) will be activated. The maximum timeout period is
0.15 seconds—see Zero Crossing Detection section.
0Fh
SAGCYC
R/W 8
FFh
Sag Line Cycle Register. This 8-bit register specifies the number of
consecutive half-line cycles the signal on Channel 2 must be below
SAGLVL before the SAG output is activated—see Voltage Sag
Detection section.
10h
IRQEN
R/W 8
40h
Interrupt Enable Register. ADE7759 interrupts may be deactivated at
any time by setting the corresponding bit in this 8-bit enable register to
Logic 0. The status register will continue to register an interrupt event
even if disabled. However, the IRQ output will not be activated—see
Interrupts section.
11h
SAGLVL
R/W 8
0h
Sag Voltage Level. An 8-bit write to this register determines at what
peak signal level on Channel 2 the SAG pin will become active. The
signal must remain low for the number of cycles specified in the
SAGCYC register before the SAG pin is activated—see Line Voltage
Sag Detection section.
12h
TEMP
R
8
0h
Temperature Register. This is an 8-bit register which contains the
result of the latest temperature conversion—see Temperature
Measurement section.
13h
LINECYC
R/W 4
3FFFh
Line Cycle Energy Accumulation Mode Half-Cycle Register. This
14-bit register is used during line cycle energy accumulation mode to
set the number of half-line cycles active energy is accumulated—see
Line Cycle Energy Accumulation Mode section.
14h
LENERGY
R
40
0h
Line Cycle Energy Accumulation Mode Active Energy Register. This
40-bit register accumulates active energy during line cycle energy
accumulation mode. The number of half-line cycles is set by the
LINECYC register—see Line Cycle Energy Accumulation Mode section.
15h
CFNUM
R/W 2
0h
CF Frequency Divider Numerator Register. The output frequency on
the CF pin is adjusted by writing to this 12-bit read/write register—see
Energy to Frequency Conversion section .
1Eh
CHKSUM
R
6
0h
Checksum Register. This 6-bit read-only register is equal to the sum of
all the ones in the previous read—see Serial Read Operation section .
1Fh
DIEREV
R
8
01h
Die Revision Register. This 8-bit read-only register contains the revision
number of the silicon.
REV. A
–29 –
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