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参数资料
| 型号： | ADE7878ACPZ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 模拟信号调理 |
| 英文描述： | Poly Phase Multifunction Energy Metering IC With Total And Fundamental Powers, No Of Pins: 40, Temperature Range: Ind |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC40 |
| 封装： | 6 X 6 MM, ROHS COMPLIANT, MO-220WJJD, LFCSP-40 |
| 文件页数： | 62/96页 |
| 文件大小： | 1096K |
| 代理商： | ADE7878ACPZ |
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ADE7854/ADE7858/ADE7868/ADE7878
Rev. E | Page 65 of 96
JUMP
TO ISR
GLOBAL
INTERRUPT
MASK
CLEAR MCU
INTERRUPT
FLAG
READ
STATUSx
JUMP
TO ISR
WRITE
BACK
STATUSx
ISR ACTION
(BASED ON STATUSx CONTENTS)
ISR RETURN
GLOBAL INTERRUPT
MASK RESET
MCU
INTERRUPT
FLAG SET
PROGRAM
SEQUENCE
t1
t2
t3
IRQx
0
85
10
-0
57
Figure 79. Interrupt Management
JUMP
TO ISR
GLOBAL
INTERRUPT
MASK
CLEAR MCU
INTERRUPT
FLAG
READ
STATUSx
READ
PHx
JUMP
TO ISR
WRITE
BACK
STATUSx
ISR ACTION
(BASED ON STATUSx CONTENTS)
ISR RETURN
GLOBAL INTERRUPT
MASK RESET
MCU
INTERRUPT
FLAG SET
PROGRAM
SEQUENCE
t1
t2
t3
IRQx
08
51
0-
0
58
Figure 80. Interrupt Management when PHSTATUS, IPEAK, VPEAK, or PHSIGN Registers are Involved
status register is read immediately to identify the phase that
triggered the interrupt. The name, PHx, in Figure 80 denotes
one of the PHSTATUS, IPEAK, VPEAK, or PHSIGN registers.
Then, STATUSx is written back to clear the status flag(s).
SERIAL INTERFACES
The ADE7854/ADE7858/ADE7868/ADE7878 have three serial
port interfaces: one fully licensed I2C interface, one serial
peripheral interface (SPI), and one high speed data capture port
(HSDC). As the SPI pins are multiplexed with some of the pins
of the I2C and HSDC ports, the ADE78xx accepts two confi-
gurations: one using the SPI port only and one using the I2C
port in conjunction with the HSDC port.
Serial Interface Choice
After reset, the HSDC port is always disabled. Choose between
the I2C and SPI ports by manipulating the SS/HSA pin after
power-up or after a hardware reset. If the SS/HSA pin is kept
high, then the ADE7854/ADE7858/ADE7868/ADE7878 use the
I2C port until a new hardware reset is executed. If the SS/HSA
pin is toggled high to low three times after power-up or after a
hardware reset, the ADE7854/ADE7858/ADE7868/ADE7878
use the SPI port until a new hardware reset is executed. This
manipulation of the SS/HSA pin can be accomplished in two
ways. First, use the SS/HSA pin of the master device (that is, the
microcontroller) as a regular I/O pin and toggle it three times.
Second, execute three SPI write operations to a location in the
address space that is not allocated to a specific ADE78xx register
(for example 0xEBFF, where eight bit writes can be executed).
These writes allow the SS/HSA pin to toggle three times. See the
section for details on the write protocol
involved.
After the serial port choice is completed, it needs to be locked.
Consequently, the active port remains in use until a hardware
reset is executed in PSM0 normal mode or until a power-down.
If I2C is the active serial port, Bit 1 (I2C_LOCK) of the CONFIG2
register must be set to 1 to lock it in. From this moment, the
ADE7854/ADE7858/ADE7868/ADE7878 ignore spurious
toggling of the SS pin and an eventual switch into using the SPI
port is no longer possible. If the SPI is the active serial port, any
write to the CONFIG2 register locks the port. From this moment,
a switch into using the I2C port is no longer possible. Once locked,
the serial port choice is maintained when the ADE78xx changes
PSMx power modes.
The functionality of the ADE78xx is accessible via several on-
chip registers. The contents of these registers can be updated or
read using either the I2C or SPI interfaces. The HSDC port provides
the state of up to 16 registers representing instantaneous values of
phase voltages and neutral currents, and active, reactive, and
apparent powers.
I2C-Compatible Interface
The ADE7854/ADE7858/ADE7868/ADE7878 supports a fully
licensed I2C interface. The I2C interface is implemented as a full
hardware slave. SDA is the data I/O pin, and SCL is the serial
clock. These two pins are shared with the MOSI and SCLK pins
of the on-chip SPI interface. The maximum serial clock frequency
supported by this interface is 400 kHz.
The two pins used for data transfer, SDA and SCL, are confi-
gured in a wire-AND’ed format that allows arbitration in a
multimaster system.
The transfer sequence of an I2C system consists of a master device
initiating a transfer by generating a start condition while the bus
is idle. The master transmits the address of the slave device and
the direction of the data transfer in the initial address transfer. If
the slave acknowledges, the data transfer is initiated. This con-
tinues until the master issues a stop condition, and the bus
becomes idle.
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