参数资料
型号: ADF4112BRUZ
厂商: Analog Devices Inc
文件页数: 12/28页
文件大小: 0K
描述: IC SYNTH PLL RF 3.0GHZ 16-TSSOP
标准包装: 96
类型: 时钟/频率合成器,RF
PLL:
输入: CMOS,TTL
输出: 时钟
电路数: 1
比率 - 输入:输出: 2:1
差分 - 输入:输出: 是/无
频率 - 最大: 3GHz
除法器/乘法器: 是/无
电源电压: 2.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
产品目录页面: 551 (CN2011-ZH PDF)
配用: EVAL-ADF4112EBZ1-ND - BOARD EVAL FOR ADF4112
EVAL-ADF411XEBZ1-ND - BOARD EVAL FOR ADF411X NO CHIP
ADF4110/ADF4111/ADF4112/ADF4113
Data Sheet
Rev. F | Page 2 of 28
TABLE OF CONTENTS
REVISION HISTORY
1/13—Rev. E to Rev. F
Changes to Table 1.............................................................................4
Changes to Ordering Guide ...........................................................28
8/12—Rev. D to Rev. E
Changed CP-20-1 to CP-20-6 ...........................................Universal
Updated Outline Dimensions........................................................28
Changes to Ordering Guide ...........................................................28
5/12—Rev. C to Rev. D
Changes to Figure 2...........................................................................5
Changes to Figure 4 and Table 4......................................................7
Updated Outline Dimensions........................................................28
Changes to Ordering Guide ...........................................................28
3/04—Data sheet changed from Rev. B to Rev. C.
Updated Format..................................................................Universal
Changes to Specifications.................................................................2
Changes to Figure 32.......................................................................22
Changes to the Ordering Guide.....................................................28
3/03—Data sheet changed from Rev. A to Rev. B.
Edits to Specifications.......................................................................2
Updated OUTLINE DIMENSIONS .............................................24
1/01—Data sheet changed from Rev. 0 to Rev. A.
Changes to DC Specifications in B Version, B Chips,
Unit, and Test Conditions/Comments Columns .....................2
Changes to Absolute Maximum Rating .........................................4
Changes to FRINA Function Test .....................................................5
Changes to Figure 8...........................................................................7
New Graph Added—TPC 22 ...........................................................9
Change to PD Polarity Box in Table V .........................................15
Change to PD Polarity Box in Table VI........................................16
Change to PD Polarity Paragraph .................................................17
Addition of New Material
(PCB Design Guidelines for Chip–Scale package) ................23
Replacement of CP-20 Outline with CP-20 [2] Outline ............24
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