参数资料
型号: ADF4156BRUZ
厂商: Analog Devices Inc
文件页数: 12/24页
文件大小: 0K
描述: IC PLL FRAC-N FREQ SYNTH 16TSSOP
产品变化通告: Improve Phase Noise Performance
设计资源: Low-Noise Microwave fractional-N PLL using active loop filter and RF prescaler (CN0174)
标准包装: 96
类型: 分数 N 合成器(RF)
PLL:
输入: CMOS,TTL
输出: 时钟
电路数: 1
比率 - 输入:输出: 2:1
差分 - 输入:输出: 是/无
频率 - 最大: 6.2GHz
除法器/乘法器: 是/是
电源电压: 2.7 V ~ 3.3 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-TSSOP(0.173",4.40mm 宽)
供应商设备封装: 16-TSSOP
包装: 管件
产品目录页面: 551 (CN2011-ZH PDF)
ADF4156
Data Sheet
Rev. E | Page 2 of 24
TABLE OF CONTENTS
REVISION HISTORY
10/13—Rev. D. to Rev. E
Changes to Table 3............................................................................ 5
Updated Outline Dimensions ....................................................... 22
Changes to Ordering Guide .......................................................... 22
3/12—Rev. C to Rev. D
Changes to Table 1............................................................................ 3
Changes to Ordering Guide .......................................................... 22
9/11—Rev. B to Rev. C
Changes to Noise Characteristics Parameter................................ 3
4/11—Rev. A to Rev. B
Changes to Product Title, Features Section and General
Description Section.......................................................................... 1
Changes to RF Input Frequency RFIN Parameter, Table 1........... 3
Changes to Figure 4 and Table 5..................................................... 6
5/09—Rev. 0 to Rev. A
Added Low Power Sleep Mode Parameter and Changes to
Endnote 4, Table 1 ............................................................................ 3
Change to Figure 9 Caption ............................................................ 7
Change to Program Modes Section ................................................9
Changes to Figure 16...................................................................... 10
Changes to Figure 17...................................................................... 11
Changes to CSR Enable Section ................................................... 13
Changes to Figure 19...................................................................... 14
Changes to Function Register, R3 Section and Figure 20 ......... 15
Changes to 12-Bit Clock Divider Value Section, to
Clock Divider Mode Section, and to Figure 21.......................... 16
Changes to Reference Doubler and Reference Divider Section
and to Fast Lock Times with the ADF4156 Section .................. 17
Added Figure 22 and Figure 23; Renumbered Sequentially ..... 19
Change to Phase Resync Section.................................................. 20
Changes to Interfacing Section and to PCB Design Guidelines
for Chip Scale Package Section..................................................... 21
Changes to Outline Dimensions .................................................. 23
Changes to Ordering Guide.......................................................... 23
5/06—Revision 0: Initial Version
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