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| 型号： | ADF4158WCCPZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 35/36页 |
| 文件大小： | 0K |
| 描述： | IC FRAC-N FREQ SYNTH 24LFCSP |
| 标准包装： | 1,500 |
| 类型： | 分数 N 合成器（RF） |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 2:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 6.1GHz |
| 除法器/乘法器： | 是/是 |
| 电源电压： | 2.7 V ~ 3.3 V |
| 工作温度： | -40°C ~ 125°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-WFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 24-LFCSP-WQ（4x4） |
| 包装： | 带卷 (TR) |
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ADF4158
Data Sheet
Rev. G | Page 8 of 36
PIN CONFIGURATION AND PIN FUNCTION DESCRIPTIONS
PIN 1
INDICATOR
1
CPGND
NOTES
1. THE LFCSP HAS AN EXPOSED PADDLE THAT MUST BE CONNECTED TO GND.
2
AGND
3
AGND
4
RFINB
5
RFINA
6
AVDD
15 DATA
16 LE
17 MUXOUT
18 SDVDD
14 CLK
13 CE
7
A
V
DD
8
A
V
DD
9
RE
F
IN
1
S
DG
ND
12
TX
D
AT
A
10
DG
ND
21
SW
2
22
V
P
23
R
SET
24
C
P
20
SW
1
19
DV
DD
ADF4158
TOP VIEW
(Not to Scale)
08728-
003
Figure 5. Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Mnemonic
Description
1
CPGND
Charge Pump Ground. This is the ground return path for the charge pump.
2, 3
AGND
Analog Ground. This is the ground return path of the prescaler.
4
RFINB
Complementary Input to the RF Prescaler. Decouple this point to the ground plane with a small bypass capacitor,
typically 100 pF.
5
RFINA
Input to the RF Prescaler. This small signal input is normally ac-coupled from the VCO.
6, 7, 8
AVDD
Positive Power Supply for the RF Section. Place decoupling capacitors to the digital ground plane as close as possible
to this pin. AVDD must have the same voltage as DVDD.
9
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input resistance of 100 kΩ.
It can be driven from a TTL or CMOS crystal oscillator, or it can be ac-coupled.
10
DGND
Digital Ground.
11
SDGND
Digital Σ-Δ Modulator Ground. Ground return path for the Σ-Δ modulator.
12
TXDATA
Tx Data Pin. Provide data to be transmitted in FSK or PSK mode on this pin.
13
CE
Chip Enable. A logic low on this pin powers down the device and puts the charge pump output into three-state mode.
14
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is latched into the shift
register on the CLK rising edge. This input is a high impedance CMOS input.
15
DATA
Serial Data Input. The serial data is loaded MSB first with the three LSBs being the control bits. This input is a high
impedance CMOS input.
16
LE
Load Enable, CMOS Input. When LE is high, the data stored in the shift registers is loaded into one of the eight latches,
with the latch being selected using the control bits.
17
MUXOUT
Multiplexer Output. This pin allows either the RF lock detect, the scaled RF, or the scaled reference frequency to be
accessed externally.
18
SDVDD
Power Supply Pin for the Digital Σ-Δ Modulator. This pin should be the same voltage as AVDD. Place decoupling
capacitors to the ground plane as close as possible to this pin.
19
DVDD
Positive Power Supply for the Digital Section. Place decoupling capacitors to the digital ground plane as close as
possible to this pin. DVDD must have the same voltage as AVDD.
20 , 21
SW1, SW2
Switches for Fast Lock.
22
VP
Charge Pump Power Supply. This should be greater than or equal to VDD. In systems where VDD is 3 V, it can be set to
5.5 V and used to drive a VCO with a tuning range of up to 5.5 V.
23
RSET
Connecting a resistor between this pin and ground sets the maximum charge pump output current. The relationship
between ICP and RSET is
SET
CPmax
R
I
5
.
25
=
where:
ICPmax = 5 mA.
RSET = 5.1 kΩ.
24
CP
Charge Pump Output. When enabled, this provides ±ICP to the external loop filter, which in turn drives the external VCO.
25
EPAD
Exposed Paddle. The LFCSP has an exposed paddle that must be connected to GND.
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