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参数资料
| 型号： | ADF4212BRUZ-RL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/20页 |
| 文件大小： | 0K |
| 描述： | IC PLL FREQ SYNTHESIZER 20-TSSOP |
| 标准包装： | 1,000 |
| 类型： | 时钟/频率合成器（RF/IF） |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 3:1 |
| 差分 - 输入:输出： | 是/无 |
| 频率 - 最大： | 2.7GHz |
| 除法器/乘法器： | 无/无 |
| 电源电压： | 2.7 V ~ 5.5 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 20-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 20-TSSOP |
| 包装： | 带卷 (TR) |
REV. A
ADF4210/ADF4211/ADF4212/ADF4213
–5–
PIN FUNCTION DESCRIPTIONS
Pin Number
TSSOP
Mnemonic
Function
1VDD1
Power Supply for the RF Section. Decoupling capacitors to the ground plane should be placed as
close as possible to this pin. VDD1 should have a value of between 2.7 V and 5.5 V. VDD1 must have
the same potential as VDD2.
2VP1
Power Supply for the RF Charge Pump. This should be greater than or equal to VDD1. In systems where
VDD1 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.
3CPRF
Output from the RF Charge Pump. This is normally connected to a loop lter which drives the input
to an external VCO.
4
DGNDRF
Ground Pin for the RF Digital Circuitry.
5RFIN
Input to the RF Prescaler. This low level input signal is ac-coupled from the RF VCO.
6
AGNDRF
Ground Pin for the RF Analog Circuitry.
7FLO
RF/IF Fastlock Mode.
8
REFIN
Reference Input. This is a CMOS input with a nominal threshold of VDD/2 and an equivalent input
resistance of 100 k
. This input can be driven from a TTL or CMOS crystal oscillator.
9
DGNDIF
Digital Ground for the IF Digital, Interface and Control Circuitry.
10
MUXOUT
This multiplexer output allows either the IF/RF Lock Detect, the scaled RF, scaled IF or the scaled
Reference Frequency to be accessed externally.
11
CLK
Serial Clock Input. This serial clock is used to clock in the serial data to the registers. The data is
latched into the 24-bit shift register on the CLK rising edge. This input is a high impedance
CMOS input.
12
DATA
Serial Data Input. The serial data is loaded MSB rst with the two LSBs being the control bits. This
input is a high impedance CMOS input.
13
LE
Load Enable, CMOS Input. When LE goes high, the data stored in the shift registers is loaded into
one of the four latches, the latch being selected using the control bits.
14
RSET
Connecting a resistor between this pin and ground sets the maximum RF and IF charge pump output
current. The nominal voltage potential at the RSET pin is 0.66 V. The relationship between ICP and RSET is
I
R
CP MAX
SET
=
13 5
.
So, with RSET = 2.7 k
, I
CP MAX = 5 mA for both the RF and IF Charge Pumps.
15
AGNDIF
Ground Pin for the IF Analog Circuitry.
16
IFIN
Input to the RF Prescaler. This low-level input signal is ac-coupled from the IF VCO.
17
DGNDIF
Ground Pin for the IF Digital, Interface, and Control Circuitry.
18
CPIF
Output from the IF Charge Pump. This is normally connected to a loop lter which drives the input
to an external VCO.
19
VP2
Power Supply for the IF Charge Pump. This should be greater than or equal to VDD2. In systems where
VDD2 is 3 V, it can be set to 6 V and used to drive a VCO with a tuning range up to 6 V.
20
VDD2
Power Supply for the IF, Digital and Interface Section. Decoupling capacitors to the ground plane should
be placed as close as possible to this pin. VDD2 should have a value of between 2.7 V and 5.5 V. VDD2
must have the same potential as VDD1.
PIN CONFIGURATIONS
TSSOP
TOP VIEW
(Not to Scale)
20
19
18
17
16
15
14
13
12
11
1
2
3
4
5
6
7
8
9
10
DATA
CLK
MUXOUT
DGNDRF
RFIN
AGNDRF
DGNDIF
REFIN
FLO
LE
RSET
AGNDIF
VDD1
VDD2
VP2
IFIN
DGNDIF
CPIF
VP1
CPRF
ADF4210/
ADF4211/
ADF4212/
ADF4213
CP-20
1
2
3
4
5
AGNDRF
FLO
CPRF
RFIN
DGNDRF
V
DD
2
V
P
2
CP
IF
V
P
1
V
DD
1
20
19
18
17
16
15
14
13
12
11
DGNDIF
IFIN
LE
RSET
AGNDIF
6
7
8
9
10
REF
IN
DGND
IF
MUXOUT
DATA
CLK
TOP VIEW
(Not to Scale)
ADF4210/
ADF4211/
ADF4212/
ADF4213
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