参数资料
| 型号： | ADF4360-1BCPZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/24页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER VCO 24-LFCSP |
| 标准包装： | 1 |
| 类型： | 扇出配送，整数-N，合成器（RF） |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 2.45GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 24-LFCSP-VQ（4x4） |
| 包装： | 托盘 |
| 产品目录页面： | 551 (CN2011-ZH PDF) |
| 配用： | EVAL-ADF4360-1EBZ1-ND - BOARD EVALUATION FOR ADF4360-1 |
Data Sheet
ADF4360-1
Rev. C | Page 19 of 24
N COUNTER LATCH
With (C2, C1) = (1, 0), the N counter latch is programmed.
Table 8 shows the input data format for programming the
N counter latch.
A Counter Latch
A5 to A1 program the 5-bit A counter. The divide range is 0
(00000) to 31 (11111).
Reserved Bits
DB7 is a spare bit that is reserved. It should be programmed to 0.
B Counter Latch
B13 to B1 program the B counter. The divide range is 3
(00.....0011) to 8191 (11....111).
Overall Divide Range
The overall divide range is defined by ((P × B) + A), where P is
the prescaler value.
CP Gain
DB21 of the N counter latch in the ADF4360 family is the
charge pump gain bit. When this is programmed to 1, Current
Setting 2 is used. When programmed to 0, Current Setting 1 is
used. This bit can also be programmed through DB10 of the con-
trol latch. The bit will always reflect the latest value written to it,
whether this is through the control latch or the N counter latch.
Divide-by-2
DB22 is the divide-by-2 bit. When set to 1, the output divide-by-2
function is chosen. When it is set to 0, normal operation occurs.
Divide-by-2 Select
DB23 is the divide-by-2 select bit. When programmed to 1, the
divide-by-2 output is selected as the prescaler input. When set
to 0, the fundamental is used as the prescaler input. For exam-
ple, using the output divide-by-2 feature and a PFD frequency
of 200 kHz, the user will need a value of N = 12,000 to generate
1.2 GHz. With the divide-by-2 select bit high, the user may keep
N = 6,000.
R COUNTER LATCH
With (C2, C1) = (0, 1), the R counter latch is programmed.
Table 9 shows the input data format for programming the
R counter latch.
R Counter
R1 to R14 set the counter divide ratio. The divide range is 1
(00......001) to 16383 (111......111).
Antibacklash Pulse Width
DB16 and DB17 set the antibacklash pulse width.
Lock Detect Precision
DB18 is the lock detect precision bit and sets the number of
reference cycles with less than 15 ns phase error for entering the
locked state. With LDP at 1, five cycles are taken, and with LDP
at 0, three cycles are taken.
Test Mode Bit
DB19 is the test mode bit (TMB) and should be set to 0. With
TMB = 0, the contents of the test mode latch are ignored and
normal operation occurs as determined by the contents of the
control latch, R counter latch, and N counter latch. Note that
test modes are for factory testing only and should not be pro-
grammed by the user.
Band Select Clock
These bits set a divider for the band select logic clock input. The
output of the R counter is by default the value used to clock the
band select logic, but if this value is too high (>1 MHz), a
divider can be switched on to divide the R counter output to a
smaller value (see Table 9).
Reserved Bits
DB23 to DB22 are spare bits that are reserved. They should be
programmed to 0.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| ADF4360-1BCPZ | 制造商:Analog Devices 功能描述:INTEGRATED SYNTHESIZER |
| ADF4360-1BCPZ | 制造商:Analog Devices 功能描述:IC FREQ SYNTHESIZER 2450MHZ 24-LFCSP |
| ADF4360-1BCPZRL | 功能描述:IC SYNTHESIZER VCO 24LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4360-1BCPZRL7 | 功能描述:IC SYNTHESIZER VCO 24LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:1,000 系列:Precision Edge® 类型:时钟/频率合成器 PLL:无 输入:CML，PECL 输出:CML 电路数:1 比率 - 输入:输出:2:1 差分 - 输入:输出:是/是 频率 - 最大:10.7GHz 除法器/乘法器:无/无 电源电压:2.375 V ~ 3.6 V 工作温度:-40°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-VFQFN 裸露焊盘，16-MLF? 供应商设备封装:16-MLF?（3x3） 包装:带卷 (TR) 其它名称:SY58052UMGTRSY58052UMGTR-ND |
| ADF4360-1SP1BCPZ | 制造商:Analog Devices 功能描述: |
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