参数资料
| 型号： | ADF4360-7BCPZRL7 |
| 厂商： | Analog Devices Inc |
| 文件页数： | 17/28页 |
| 文件大小： | 0K |
| 描述： | IC SYNTHESIZER VCO 24LFCSP |
| 标准包装： | 1,500 |
| 类型： | 扇出配送，整数-N，合成器（RF） |
| PLL： | 是 |
| 输入： | CMOS，TTL |
| 输出： | 时钟 |
| 电路数： | 1 |
| 比率 - 输入:输出： | 1:2 |
| 差分 - 输入:输出： | 无/无 |
| 频率 - 最大： | 1.8GHz |
| 除法器/乘法器： | 是/无 |
| 电源电压： | 3 V ~ 3.6 V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 24-VFQFN 裸露焊盘，CSP |
| 供应商设备封装： | 24-LFCSP-VQ（4x4） |
| 包装： | 带卷 (TR) |
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ADF4360-7
Data Sheet
Rev. D | Page 24 of 28
OUTPUT MATCHING
There are a number of ways to match the output of the
ADF4360-7 for optimum operation; the most basic is to use a
50 resistor to VVCO. A dc bypass capacitor of 100 pF is con-
nected in series, as shown in Figure 29. Because the resistor is
not frequency dependent, this provides a good broadband
match. The output power in this circuit typically gives
5 dBm output power into a 50 load.
100pF
04441-033
RFOUT
VVCO
50
51
Figure 29. Simple ADF4360-7 Output Stage
A better solution is to use a shunt inductor (acting as an RF
choke) to VVCO. This gives a better match and, therefore, more
output power. Additionally, a series inductor is added after the
dc bypass capacitor to provide a resonant LC circuit. This tunes
the oscillator output and provides approximately 10 dB addi-
tional rejection of the second harmonic. The shunt inductor
needs to be a relatively high value (>40 nH).
Experiments have shown that the circuit shown in Figure 30
provides an excellent match to 50 over a limited operating
range of the ADF4360-7 (850 MHz to 950 MHz). This gives
approximately 2 dBm output power across the specific
frequency range of the ADF4360-7 using 3.9 nH. For other
frequencies, a tuned LC is recommended. Both complementary
architectures can be examined using the EV-ADF4360-7EB1Z
evaluation board.
7.5nH
47nH
3.9pF
04441-034
RFOUT
VVCO
50
Figure 30. Optimum ADF4360-7 Output Stage
If the user does not need the differential outputs available
on the ADF4360-7, the user may either terminate the unused
output or combine both outputs using a balun. The circuit in
Figure 31 shows how best to combine the outputs.
7.5nH
9.0nH
47nH
9.0nH
3.3pF
100pF
3.3pF
50
7.5nH
RFOUTA
VVCO
RFOUTB
04441-035
Figure 31. Balun for Combining ADF4360-7 RF Outputs
The circuit in Figure 31 is a lumped-lattice-type LC balun. It
is designed for a center frequency of 900 MHz and outputs
5.0 dBm at this frequency. The series 7.5 nH inductor is used to
tune out any parasitic capacitance due to the board layout from
each input, and the remainder of the circuit is used to shift the
output of one RF input by +90° and the second by 90°, thus
combining the two. The action of the 9.0 nH inductor and the
3.3 pF capacitor accomplishes this. The 47 nH is used to pro-
vide an RF choke to feed the supply voltage, and the 100 pF
capacitor provides the necessary dc block. To ensure good RF
performance, the circuits in Figure 30 and Figure 31 are imple-
mented with Coilcraft 0402/0603 inductors and AVX 0402 thin-
film capacitors.
Alternatively, instead of the LC balun shown in Figure 31, both
outputs may be combined using a 180° rat-race coupler.
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| ADF4360-8 | 制造商:AD 制造商全称:Analog Devices 功能描述:Integrated Synthesizer and VCO |
| ADF4360-8BCP | 制造商:Analog Devices 功能描述:Integrated Synthesizer 24-Pin LFCSP EP 制造商:Analog Devices 功能描述:INTEGRATED SYNTHESIZER 24LFCSP - Trays 制造商:Analog Devices 功能描述:IC SYNTHESIZER PLL |
| ADF4360-8BCPRL | 制造商:Analog Devices 功能描述:Integrated Synthesizer 24-Pin LFCSP EP T/R |
| ADF4360-8BCPRL7 | 制造商:Analog Devices 功能描述:Integrated Synthesizer 24-Pin LFCSP EP T/R |
| ADF4360-8BCPZ | 功能描述:IC SYNTHESIZER VCO 24-LFCSP RoHS:是 类别:集成电路 (IC) >> 时钟/计时 - 时钟发生器，PLL，频率合成器 系列:- 标准包装:2,000 系列:- 类型:PLL 频率合成器 PLL:是 输入:晶体 输出:时钟 电路数:1 比率 - 输入:输出:1:1 差分 - 输入:输出:无/无 频率 - 最大:1GHz 除法器/乘法器:是/无 电源电压:4.5 V ~ 5.5 V 工作温度:-20°C ~ 85°C 安装类型:表面贴装 封装/外壳:16-LSSOP（0.175"，4.40mm 宽） 供应商设备封装:16-SSOP 包装:带卷 (TR) 其它名称:NJW1504V-TE1-NDNJW1504V-TE1TR |
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