参数资料
型号: ADF4360-7BCPZRL7
厂商: Analog Devices Inc
文件页数: 8/28页
文件大小: 0K
描述: IC SYNTHESIZER VCO 24LFCSP
标准包装: 1,500
类型: 扇出配送,整数-N,合成器(RF)
PLL:
输入: CMOS,TTL
输出: 时钟
电路数: 1
比率 - 输入:输出: 1:2
差分 - 输入:输出: 无/无
频率 - 最大: 1.8GHz
除法器/乘法器: 是/无
电源电压: 3 V ~ 3.6 V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 24-VFQFN 裸露焊盘,CSP
供应商设备封装: 24-LFCSP-VQ(4x4)
包装: 带卷 (TR)
ADF4360-7
Data Sheet
Rev. D | Page 16 of 28
Table 9. R Counter Latch
DB20 DB19 DB18 DB17 DB16 DB15 DB14 DB13 DB12 DB11 DB10
DB9
DB8
DB7
DB6
DB5
DB4
DB3
DB2
DB1
DB0
C2 (0) C1 (1)
R1
R2
R3
R4
R5
R7
R8
R9
R10
R11
R12
R13
R14
ABP1
ABP2
LDP
TMB
BSC1
R6
CONTROL
BITS
BAND
SELECT
CLOCK
ANTI-
BACKLASH
PULSE
WIDTH
14-BIT REFERENCE COUNTER
DB21
DB22
DB23
LOCK
DETECT
PRECISION
TEST
MODE
BIT
RESERVED
BSC2
RSV
TEST MODE
BIT SHOULD
BE SET TO 0
FOR NORMAL
OPERATION.
R14
R13
R12
R3
R2
R1
DIVIDE RATIO
..........
0
1
..........
0
1
0
2
..........
0
1
3
..........
1
0
4
..........
.
..........
.
..........
.
..........
1
0
16380
..........
1
0
1
16381
..........
1
0
16382
..........
1
16383
THESE BITS ARE NOT
USED BY THE DEVICE
AND ARE DON'T CARE
BITS.
04441-025
LDP
LOCK DETECT PRECISION
0
THREE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
1
FIVE CONSECUTIVE CYCLES OF PHASE DELAY LESS THAN
15ns MUST OCCUR BEFORE LOCK DETECT IS SET.
ABP2
ABP1
ANTIBACKLASH PULSE WIDTH
0
3.0ns
0
1
1.3ns
1
0
6.0ns
1
3.0ns
BSC2
BSC1
BAND SELECT CLOCK DIVIDER
0
1
0
1
2
1
0
4
1
8
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