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参数资料
| 型号： | ADF4602BCPZ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Single-Chip, Multiband 3G Femtocell Transceiver; Package: LFCSP: Leadform Chip Scale; No of Pins: 40; Temperature Range: Ind |
| 中文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC40 |
| 封装： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40 |
| 文件页数： | 20/36页 |
| 文件大小： | 646K |
| 代理商： | ADF4602BCPZ |
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ADF4602
Rev. A | Page 27 of 36
REGISTER DESCRIPTION
Table 10. General User Registers
Register
Bit
Bit Name
Description
13
rxen
Set this bit high to enable the receiver. A low here disables the receiver.
1, A1,
Write
12
refclken
Setting this bit high enables the 26 MHz reference output buffer.
11
chipclken
Setting this bit high enables the19.2 MHz chip clock output buffer.
[10:6]
ldoen
The on-chip LDOs are powered down individually. For normal operation all LDOs should be enabled
(Bits[10 : 6] = [11111])
ldoen[10:6]1
Mode
XXXX1
VSUP1 2.6 V enable
XXX1X
VSUP2 2.8 V enable
XX1XX
VSUP3 1.8 V enable
X1XXX
VSUP4 2.6 V enable
1XXXX
VSUP5 2.8 V enable
5
txen
Setting this bit high enables the transmitter.
4
txbs
This bit controls which of the transmit outputs is in use. 0 = low band (TXLBRF), 1 = high band (TXHBRF).
3
txsynthen
Setting this bit high enables the transmit synthesizer.
[2:1]
rxbs
These bits control the receiver band select.
rxbs[2:1]
Operation
00
Reserved
01
Low band enable (RXLBRF)
10
High Band 1 enable (RXHB1RF) (default)
11
High Band 2 enable (RXHB2RF)
0
rxsynthen
Setting this bit high enables the receive synthesizer
2, A1,
Write
1
sif_vsup8
The serial port readback (SDATA) output voltage is changed from 1.8 V to 2.8 V with this bit. 0 = use 1.8 V
VINT supply, 1 = use 2.8 V VSUP8 supply. After power-up or after a soft reset, the ADF4602 defaults to 2.8 V
readback mode.
0
reset_soft
A rising edge on this bit starts a 50 μs reset pulse for the full chip. This bit is self clearing. It is
recommended that a soft reset be performed after power-up.
1 X = don’t care.
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