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参数资料
| 型号： | ADF4602BCPZ |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 无绳电话/电话 |
| 英文描述： | Single-Chip, Multiband 3G Femtocell Transceiver; Package: LFCSP: Leadform Chip Scale; No of Pins: 40; Temperature Range: Ind |
| 中文描述： | TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC40 |
| 封装： | 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40 |
| 文件页数： | 24/36页 |
| 文件大小： | 646K |
| 代理商： | ADF4602BCPZ |
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ADF4602
Rev. A | Page 30 of 36
Register
Bit
Bit Name
Description
28, A1
Write
[15:4]
txpwr_set
Requested transmit power at antenna. LSB = 1/32 dBm, 0x000 = 80 dBm, 0xFFF = 47.96875 dBm.
The output power is referenced to a full scale sine wave applied to the transmit baseband inputs.
For WCDMA modulated signals, the output power measured in a 3.84 MHz bandwidth is reduced
by the peak to average ratio of the signal. See the I/Q Modulator section for more details. The valid
range of transmit output power setting is 80 dBm to +10 dBm. Output clipping may occur sooner,
depending on the PAR of the applied signal.
The txpwr_set register should be updated periodically, or with every 5°C change in temperature to
ensure accurate output power. See the VCO Output section for more details.
0
Set this bit to 1 to control the output power from the txpwr_set bits.
31, A1
Write
4
nvmld
Setting this bit to 1 triggers a manual load of the nonvolatile memory contents. See the Software
Initialization Procedure section for more details.
31, A1
Read
[7:0]
revid
Chip Revision ID. Revision represented in hex value. A readback of 0x21 represents Rev 2.1.
1 X = don’t care.
Table 13. Sub-Address Registers
Register
Bit
Bit Name
Description
0.144, A2 Write
[2:1]
reserved[1:0]
These bits should be set to 11 for normal operation.
0.151, A2 Write
[7:0]
vsup2[7:0]
These bits control the VSUP2 regulator voltage and should be set to 0x6F for normal
operation. During the initialization sequence, the VSUP2 voltage is temporarily set to
3.1 V. See the Software Initialization Procedure section for more details.
0.153, A2 Write
[7:0]
reserved[7:0]
These bits should be set to 0x85 for normal operation.
0.155, A2 Write
[7:0]
reserved[7:0]
These bits should be set to 0x78 for normal operation.
0.165, A2 Write
[7:0]
reserved[7:0]
These bits should be set to 0x20 for normal operation.
0.170, A2 Write
[7:4]
en_mix[3:0]
These bits enable the I, IB, Q, and QB channels of the modulator separately. Set these bits
to all 1s to enable the modulator for normal operation.
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