参数资料
型号: ADF4602BCPZ
厂商: ANALOG DEVICES INC
元件分类: 无绳电话/电话
英文描述: Single-Chip, Multiband 3G Femtocell Transceiver; Package: LFCSP: Leadform Chip Scale; No of Pins: 40; Temperature Range: Ind
中文描述: TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, QCC40
封装: 6 X 6 MM, ROHS COMPLIANT, MO-220VJJD-2, LFCSP-40
文件页数: 21/36页
文件大小: 646K
代理商: ADF4602BCPZ
ADF4602
Rev. A | Page 28 of 36
Table 11. Receiver User Registers
Register
Bit
Name
Description
10, A1,
Write
[15:0]
rxfreq
These bits set the receive synthesizer frequency in 50 kHz steps from 0 MHz to 3276.75 MHz. For the high
bands this is equal to the channel frequency, and for the low bands it is 2× the channel frequency.
For example:
Bit 15 to Bit 0 (Hex)
RXHB1RF, RXHB2RF Synthesizer
Frequency
RXLBRF Synthesizer Frequency
0x9470
1900 MHz
950 MHz
0x9858
1950 MHz
975 MHz
[6:0]
rxgain
These bits set the receiver gain in conjunction with the gaincal[4:0] setting in register 15. LSB = 1 dB.
11, A1,
Write
0x00 = 0dB, 0x7F = 127 dB.
Gain = rxgain gaincal + X
where X is 8 in WCDMA mode and 17 in GSM mode. The mode is selected by the rxbw bits in
Register 15.
With mixstep = 6 and lnastep = 10, the valid range for rxgain is from 12 dB to 102 dB. Settings outside of
these are clipped at 12 dB and 102 dB. See Figure 45 for an example.
[15:12]
rfskip
Skip offset control state when no RF gain step occurred for State 3 to State 0. Default = 0x0 = 0.
12, A1,
Write
[11:8]
sdmen
Σ-Δ modulator enable for State 3 to State 0. Default = 0xF = 15.
[7:4]
mixstep
Gain decode threshold for mixer gain reduction step. LSB = 4 dB steps. Default = 0xA = 10.
[3:0]
lnastep
Gain decode threshold for LNA gain reduction step. LSB = 4 dB steps. Default = 0x6 = 6.
[15:12]
osadc2x
Offset measurement ADC range for State 3 to State 0. Default = 0x1 = 1.
13, A1,
Write
[11:8]
nper2
State duration for State 2. Default = 0x0 = 0.
[7:4]
nper1
State duration for State 1. Default = 0x3 = 3.
[3:0]
nper0
State duration for State 0. Default = 0xE = 14.
[15:12]
nint3
Integrator time constant for State 3. Default = 0xE = 14.
14, A1,
Write
[11:8]
nint2
Integrator time constant for State 2. Default =0xE = 14.
[7:4]
nint1
Integrator time constant for State 1. Default = 0x5 = 5.
[3:0]
nint0
Integrator time constant for State 0. Default = 0x3 = 3.
11
vcmsel
This sets the receive baseband output common-mode voltage. 0 = 1.2 V, 1 = 1.4 V.
15, A1,
Write
10
swapq
Setting this bit high swaps the differential Q outputs, RXBBQ and RXBBQB.
9
swapi
Setting this bit high swaps the differential I outputs, RXBBI and RXBBIB.
[8:6]
rxbw
This bit controls the receive baseband filter bandwidth.
rxbw [8:6]
Filter Mode
000
Fifth order WCDMA filter (not recommended for femtocells)
010
Seventh order WCDMA filter (recommended WCDMA filter for
femtocells)
111
GSM filter
Else
Reserved
[5:1]
gaincal
These bits are used for calibration of front-end loss. LSB = 1 dB, 0x00 = 0 dB, 0x1F = 31 dB. It is used in the
calculation of the receive gain. See rxgain in Register 11. If not used for calibration, this should be set to 8
in WCDMA mode and 17 in GSM mode.
0
sdmosr
Offset loop Σ-Δ modulator over sampling ratio. 1 = 4×, 0 = 2× (default)
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