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参数资料
| 型号： | ADM1024ARUZ-REEL |
| 厂商： | ON Semiconductor |
| 文件页数： | 21/30页 |
| 文件大小： | 0K |
| 描述： | IC MONITOR SYS TEMP/VOLT 24TSSOP |
| 产品变化通告： | MFG CHG Notification ADI to ON Semi |
| 标准包装： | 2,500 |
| 应用： | PC，PDA |
| 接口： | 串行 |
| 电源电压： | 2.8 V ~ 5.5 V |
| 封装/外壳： | 24-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 24-TSSOP |
| 包装： | 带卷 (TR) |
| 安装类型： | 表面贴装 |
| 其它名称： | ADM1024ARUZ-REEL-ND ADM1024ARUZ-REELOSTR |
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ADM1024
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Table 16. REGISTER 43H, INT INTERRUPT MASK REGISTER 1 (POWER-ON DEFAULT, 00H)
Bit
Name
R/W
Description
0
2.5 V/Ext. Temp2
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
1
VCCP1
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
2
VCC
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
3
5.0 V
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
4
Int. Temp
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
5
Ext. Temp1
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
6
FAN1/AIN1
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
7
FAN2/AIN2
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
Table 17. REGISTER 44H, INT INTERRUPT MASK REGISTER 2 (POWER-ON DEFAULT, 00H)
Bit
Name
R/W
Description
0
12 V
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
1
VCCP2
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
2
Reserved
R/W
Powerup Default Set to Low.
3
Reserved
R/W
Powerup Default Set to Low.
4
CI
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
5
THERM (Input)
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
6
D1 Fault
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
7
D2 Fault
R/W
A 1 disables the corresponding interrupt status bit for INT interrupt.
Table 18. REGISTER 46H, CHASSIS INTRUSION CLEAR (POWER-ON DEFAULT, 00H)
Bit
Name
R/W
Description
0–6
Reserved
Read only
Undefined, always reads as 00h.
7
Chassis Int. Clear
R/W
A 1 outputs a minimum 20 ms active low pulse on the Chassis Intrusion pin. The
register bit clears itself after the pulse has been output.
Table 19. REGISTER 47H, VID03/FAN DIVISOR REGISTER (POWER-ON DEFAULT, 0101(VID30))
Bit
Name
R/W
Description
0–3
VID
Read only
The VID<3:0> inputs from processor core power supplies to indicate the operating
voltage (e.g., 1.3 V to 3.5 V).
4–5
FAN1 Divisor
R/W
Sets counter prescaler for FAN1 speed measurement.
<5:4> = 00 – divide by 1
<5:4> = 01 – divide by 2
<5:4> = 10 – divide by 4
<5:4> = 11 – divide by 8
6–7
FAN2 Divisor
R/W
Sets counter prescaler for FAN2 speed measurement.
<7:6> = 00 – divide by 1
<7:6> = 01 – divide by 2
<7:6> = 10 – divide by 4
<7:6> = 11 – divide by 8
Table 20. REGISTER 49H, VID4/DEVICE ID REGISTER (POWER-ON DEFAULT, 1000000(VID4))
Bit
Name
R/W
Description
0
VID4
Read only
VID4 Input from Pentium
1–7
Reserved
Read only
Undefined, always reads as 1000 000(VID4)
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