参数资料
型号: ADM1026JST-REEL
厂商: ON Semiconductor
文件页数: 47/55页
文件大小: 0K
描述: IC CNTRL SYS REF/EEPROM 48LQFP
产品变化通告: MFG CHG Notification ADI to ON Semi
Product Obsolescence 30/Sept/2009
标准包装: 2,000
功能: 硬件监控器
传感器类型: 内部和外部
感应温度: 0°C ~ 100°C
精确度: ±3°C(最小值)
拓扑: ADC,比较器,多路复用器,寄存器库
输出类型: SMBus?
输出警报:
输出风扇:
电源电压: 3 V ~ 5.5 V
工作温度: 0°C ~ 100°C
安装类型: 表面贴装
封装/外壳: 48-LQFP
供应商设备封装: 48-LQFP(7x7)
包装: 带卷 (TR)
ADM1026
Table 51. REGISTER 25H, STATUS REGISTER 6 (POWER-ON DEFAULT, 00H)
Bit
0
1
2
3
4
5
6
7
Name
GPIO8 Status = 0
GPIO9 Status = 0
GPIO10 Status = 0
GPIO11 Status = 0
GPIO12 Status = 0
GPIO13 Status = 0
GPIO14 Status = 0
GPIO15 Status = 0
R/W
(Note 1)
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
Description
When GPIO8 is configured as an input, this bit is set when GPIO8 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 3.)
When GPIO8 is configured as an output, setting this bit asserts GPIO8. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 3.)
When GPIO9 is configured as an input, this bit is set when GPIO9 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 3.)
When GPIO9 is configured as an output, setting this bit asserts GPIO9. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 3.)
When GPIO10 is configured as an input, this bit is set when GPIO10 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 3.)
When GPIO10 is configured as an output, setting this bit asserts GPIO10. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 3.)
When GPIO11 is configured as an input, this bit is set when GPIO11 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 3.)
When GPIO11 is configured as an output, setting this bit asserts GPIO11. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 3.)
When GPIO12 is configured as an input, this bit is set when GPIO12 is asserted.
(Asserted may be active high or active low depending on setting of Bit 1 in GPIO
Configuration Register 4.)
When GPIO12 is configured as an output, setting this bit asserts GPIO12. (Asserted
may be active high or active low depending on setting of Bit 1 in GPIO Configuration
Register 4.)
When GPIO13 is configured as an input , this bit is set when GPIO13 is asserted.
(Asserted may be active high or active low depending on setting of Bit 3 in GPIO
Configuration Register 4.)
When GPIO13 is configured as an output, setting this bit asserts GPIO13. (Asserted
may be active high or active low depending on setting of Bit 3 in GPIO Configuration
Register 4.)
When GPIO14 is configured as an input , this bit is set when GPIO14 is asserted.
(Asserted may be active high or active low depending on setting of Bit 5 in GPIO
Configuration Register 4.)
When GPIO14 is configured as an output, setting this bit asserts GPIO14. (Asserted
may be active high or active low depending on setting of Bit 5 in GPIO Configuration
Register 4.)
When GPIO15 is configured as an input, this bit is set when GPIO15 is asserted.
(Asserted may be active high or active low depending on setting of Bit 7 in GPIO
Configuration Register 4.)
When GPIO15 is configured as an output, setting this bit asserts GPIO15. (Asserted
may be active high or active low depending on setting of Bit 7 in GPIO Configuration
Register 4.)
1. GPIO status bits can be written only when a GPIO pin is configured as output. Read-only otherwise.
Table 52. REGISTER 26H, V BAT MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit
7–0
Name
V BAT Value
R/W
R
Description
This register contains the measured value of the V BAT analog input channel.
Table 53. REGISTER 27H, A IN8 MEASURED VALUE (POWER-ON DEFAULT, 00H)
Bit
7–0
Name
A IN8 Value
R/W
R
Description
This register contains the measured value of the A IN8 analog input channel.
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