参数资料
| 型号： | ADM1063ASUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/32页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR/SEQUENCER 48-TQFP |
| 标准包装： | 1 |
| 系列： | Super Sequencer® |
| 类型： | 序列发生器 |
| 监视电压数目： | 10 |
| 输出： | 可编程 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
| 配用： | EVAL-ADM1063TQEBZ-ND - BOARD EVALUATION FOR ADM1063TQ |
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ADM1063
OUTPUTS
SUPPLY SEQUENCING THROUGH
CONFIGURABLE OUTPUT DRIVERS
Supply sequencing is achieved with the ADM1063 using the
register (see the AN-698 Application Note at www.analog.com for
details).
The data sources are as follows:
programmable driver outputs (PDOs) on the device as control
signals for supplies. The output drivers can be used as logic
enables or as FET drivers.
The sequence in which the PDOs are asserted (and, therefore,
the supplies are turned on) is controlled by the sequencing engine
(SE). The SE determines what action is taken with the PDOs,
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Output from the SE.
Directly from the SMBus. A PDO can be configured so that
the SMBus has direct control over it. This enables software
control of the PDOs. Therefore, a microcontroller can be
used to initiate a software power-up/power-down sequence.
On-chip clock. A 100 kHz clock is generated on the device.
based on the condition of the ADM1063 inputs. Therefore, the
PDOs can be set up to assert when the SFDs are in tolerance, the
correct input signals are received on the VXx digital pins, no
warnings are received from any of the inputs of the device, and
at other times. The PDOs can be used for a variety of functions.
The primary function is to provide enable signals for LDOs or
dc-to-dc converters that generate supplies locally on a board.
The PDOs can also be used to provide a PWRGD signal, when all
the SFDs are in tolerance, or a RESET output if one of the SFDs
goes out of specification (this can be used as a status signal for a
This clock can be made available on any of the PDOs. It
can be used, for example, to clock an external device such
as an LED.
DEFAULT OUTPUT CONFIGURATION
All of the internal registers in an unprogrammed ADM1063 device
from the factory are set to 0. Because of this, the PDOx pins are
pulled to GND by a weak (20 kΩ) on-chip pull-down resistor.
As the input supply to the ADM1063 ramps up on VPx or VH,
all PDOx pins behave as follows:
DSP, FPGA, or other microcontroller).
The PDOs can be programmed to pull up to a number of different
options. The outputs can be programmed as follows:
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Input supply = 0 V to 1.2 V. The PDOs are high impedance.
Input supply = 1.2 V to 2.7 V. The PDOs are pulled to GND
by a weak (20 kΩ) on-chip pull-down resistor.
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Open drain (allowing the user to connect an external
pull-up resistor).
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Supply > 2.7 V. Factory programmed devices continue to
pull all PDOs to GND by a weak (20 kΩ) on-chip pull-down
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Open drain with weak pull-up to V DD .
Open drain with strong pull-up to V DD .
Open drain with weak pull-up to VPx.
Open drain with strong pull-up to VPx.
Strong pull-down to GND.
Internally charge-pumped high drive (12 V, PDO1 to
resistor. Programmed devices download current EEPROM
configuration data, and the programmed setup is latched. The
PDO then goes to the state demanded by the configuration.
This provides a known condition for the PDOs during
power-up.
The internal pull-down can be overdriven with an external pull-
PDO6 only).
The last option (available only on PDO1 to PDO6) allows the
user to directly drive a voltage high enough to fully enhance an
external N-FET, which is used to isolate, for example, a card-
side voltage from a backplane supply (a PDO can sustain greater
than 10.5 V into a 1 μA load). The pull-down switches can also
be used to drive status LEDs directly.
The data driving each of the PDOs can come from one of three
up of suitable value tied from the PDOx pin to the required pull-up
voltage. The 20 kΩ resistor must be accounted for in calculating
a suitable value. For example, if PDOx must be pulled up to 3.3 V,
and 5 V is available as an external supply, the pull-up resistor
value is given by
3.3 V = 5 V × 20 kΩ/( R UP + 20 kΩ)
Therefore,
R UP = (100 kΩ ? 66 kΩ)/3.3 V = 10 kΩ
sources. The source can be enabled in the PDOxCFG configuration
VFET (PDO1 TO PDO6 ONLY)
VP4
V DD
SE DATA
SMBus DATA
CFG4 CFG5 CFG6
SEL
VP1
PDO
CLK DATA
Figure 22. Programmable Driver Output
Rev. C | Page 16 of 32
相关PDF资料 |
PDF描述 |
|---|---|
| ADM1064ACPZ | IC SEQUENCER/SUPERVISOR 40-LFCSP |
| ADM1065ASUZ | IC SEQUENCER/MONITOR 48-TQFP |
| ADM1066ASUZ-REEL7 | IC SEQUENCER/SUPERVISOR 48TQFP |
| ADM1067ACPZ | IC SEQUENCER/SUPERVISOR 40-LFCSP |
| ADM1068ASTZ-REEL7 | IC SEQUENCER/SUPERVISOR 32LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADM1063ASUZ-REEL7 | 功能描述:IC SEQUENCER/SUPERVISOR 48TQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 监控器 系列:Super Sequencer® 标准包装:1 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:开路漏极或开路集电极 复位:高有效 复位超时:- 电压 - 阀值:1.8V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:6-TSOP（0.059"，1.50mm 宽）5 引线 供应商设备封装:5-TSOP 包装:剪切带 (CT) 其它名称:NCP301HSN18T1GOSCT |
| ADM1064 | 制造商:AD 制造商全称:Analog Devices 功能描述:Super Sequencer with Voltage Readback ADC |
| ADM1064ACP | 制造商:Analog Devices 功能描述:Volt Supervisor Sequencer 2.7V to 5.4V 40-Pin LFCSP EP |
| ADM1064ACP-REEL | 制造商:Analog Devices 功能描述:Volt Supervisor Sequencer 2.7V to 5.4V 40-Pin LFCSP EP T/R |
| ADM1064ACP-REEL7 | 制造商:Analog Devices 功能描述:Volt Supervisor Sequencer 2.7V to 5.4V 40-Pin LFCSP EP T/R |
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