参数资料
| 型号： | ADM1063ASUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 29/32页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR/SEQUENCER 48-TQFP |
| 标准包装： | 1 |
| 系列： | Super Sequencer® |
| 类型： | 序列发生器 |
| 监视电压数目： | 10 |
| 输出： | 可编程 |
| 电压 - 阀值： | 可调节/可选择 |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 48-TQFP |
| 供应商设备封装： | 48-TQFP（7x7） |
| 包装： | 托盘 |
| 配用： | EVAL-ADM1063TQEBZ-ND - BOARD EVALUATION FOR ADM1063TQ |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页当前第29页第30页第31页第32页
ADM1063
?
An address crosses a page boundary. In this case, both
pages must be erased before programming.
8.
9.
The slave asserts an ACK on SDA.
The ADM1063 sends a byte-count data byte that tells the
master how many data bytes to expect. The ADM1063
always returns 32 data bytes (0x20), which is the maximum
Note that the ADM1063 features a clock extend function for
allowed by the SMBus Version 1.1 specification.
writes to EEPROM. Programming an EEPROM byte takes
approximately 250 μs, which limits the SMBus clock for
repeated or block write operations. The ADM1063 pulls SCL
low and extends the clock pulse when it cannot accept any
more data.
10.
11.
12.
13.
The master asserts an ACK on SDA.
The master receives 32 data bytes.
The master asserts an ACK on SDA after each data byte.
The master asserts a stop condition on SDA to end
the transaction.
READ OPERATIONS
The ADM1063 uses the following SMBus read protocols.
1
S
2
SLAVE
ADDRESS
3
W A
4
COMMAND 0xFD
(BLOCK READ)
5 6
A S
7
SLAVE
ADDRESS
8
R A
9
BYTE
COUNT
10
A
11
DATA
1
12
A
Receive Byte
In a receive byte operation, the master device receives a single
13
byte from a slave device, as follows:
1.
The master device asserts a start condition on SDA.
2.
The master sends the 7-bit slave address followed by the
read bit (high).
Figure 44. Block Read from the EEPROM or RAM
Error Correction
DATA
32
A
P
3.
4.
5.
6.
The addressed slave device asserts an ACK on SDA.
The master receives a data byte.
The master asserts a NACK on SDA.
The master asserts a stop condition on SDA, and the
The ADM1063 provides the option of issuing a packet error
correction (PEC) byte after a write to the RAM, a write to the
EEPROM, a block write to the RAM/EEPROM, or a block read
from the RAM/ EEPROM. This option enables the user to verify
transaction ends.
In the ADM1063, the receive byte protocol is used to read a
single byte of data from a RAM or EEPROM location whose
address has previously been set by a send byte or write
that the data received by or sent from the ADM1063 is correct.
The PEC byte is an optional byte sent after the last data byte has
been written to or read from the ADM1063. The protocol is the
same as for a block read for Step 1 to Step 12 and then proceeds
as follows:
1
2
3
4
5
6
13. The ADM1063 issues a PEC byte to the master. The master
S
SLAVE
ADDRESS
R
A
DATA
A
P
checks the PEC byte and issues another block read if the
PEC byte is incorrect.
Figure 43. Single Byte Read from the EEPROM or RAM
Block Read
In a block read operation, the master device reads a block of
data from a slave device. The start address for a block read must
have been set previously. In the ADM1063, this is done by a
send byte operation to set a RAM address or a write byte/word
operation to set an EEPROM address. The block read operation
itself consists of a send byte operation that sends a block read
command to the slave, immediately followed by a repeated start
and a read operation that reads out multiple data bytes, as follows:
14. A NACK is generated after the PEC byte to signal the end
of the read.
15. The master asserts a stop condition on SDA to end
the transaction.
Note that the PEC byte is calculated using CRC-8. The frame
check sequence (FCS) conforms to CRC-8 by the polynomial
C ( x ) = x 8 + x 2 + x 1 + 1
See the SMBus Version 1.1 specification for details.
An example of a block read with the optional PEC byte is shown
1.
The master device asserts a start condition on SDA.
1
2
3
4
5 6
7
8
9
10
11
12
S ADDRESS W A
(BLOCK READ) A S ADDRESS R A COUNT A
2.
The master sends the 7-bit slave address followed by the
write bit (low).
SLAVE
COMMAND 0xFD SLAVE BYTE
DATA
1
A
3.
The addressed slave device asserts an ACK on SDA.
4.
The master sends a command code that tells the slave
13 14 15
device to expect a block read. The ADM1063 command
code for a block read is 0xFD (1111 1101).
DATA
32
A PEC A P
5.
6.
7.
The slave asserts an ACK on SDA.
The master asserts a repeat start condition on SDA.
The master sends the 7-bit slave address followed by the
read bit (high).
Rev. C | Page 29 of 32
Figure 45. Block Read from the EEPROM or RAM with PEC
相关PDF资料 |
PDF描述 |
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| ADM1063ASUZ-REEL7 | 功能描述:IC SEQUENCER/SUPERVISOR 48TQFP RoHS:是 类别:集成电路 (IC) >> PMIC - 监控器 系列:Super Sequencer® 标准包装:1 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:开路漏极或开路集电极 复位:高有效 复位超时:- 电压 - 阀值:1.8V 工作温度:-40°C ~ 125°C 安装类型:表面贴装 封装/外壳:6-TSOP（0.059"，1.50mm 宽）5 引线 供应商设备封装:5-TSOP 包装:剪切带 (CT) 其它名称:NCP301HSN18T1GOSCT |
| ADM1064 | 制造商:AD 制造商全称:Analog Devices 功能描述:Super Sequencer with Voltage Readback ADC |
| ADM1064ACP | 制造商:Analog Devices 功能描述:Volt Supervisor Sequencer 2.7V to 5.4V 40-Pin LFCSP EP |
| ADM1064ACP-REEL | 制造商:Analog Devices 功能描述:Volt Supervisor Sequencer 2.7V to 5.4V 40-Pin LFCSP EP T/R |
| ADM1064ACP-REEL7 | 制造商:Analog Devices 功能描述:Volt Supervisor Sequencer 2.7V to 5.4V 40-Pin LFCSP EP T/R |
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