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参数资料
| 型号： | ADM1075-2ARUZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 11/52页 |
| 文件大小： | 0K |
| 描述： | IC CTRLR HOTSWAP -48V 28TSSOP |
| 标准包装： | 50 |
| 类型： | 热交换控制器 |
| 应用： | -48V 远程电力系统，高可用性，电信/数据通信系统 |
| 内部开关： | 无 |
| 电流限制： | 可调 |
| 电源电压： | -35 V ~ -80 V |
| 工作温度： | -40°C ~ 105°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 28-TSSOP（0.173"，4.40mm 宽） |
| 供应商设备封装： | 28-TSSOP |
| 包装： | 管件 |
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Data Sheet
PIN CONFIGURATION AND FUNCTION DESCRIPTION
OV 1
PLIM 2
ADM1075
21 SENSE–
20 VEE
DRAIN 1
VIN 2
UVH 3
28 VEE_G
27 GATE
26 SENSE+
VCAP 3
ADC_V 4
ISET 5
SS 6
TIMER 7
ADM1075
TOP VIEW
(Not to Scale)
19 SPLYGD
18 ADC_AUX
17 PWRGD
16 SCL
15 SDAI
UVL 4
25 SENSE–
OV 5
PLIM 6
VCAP 7
ADC_V 8
ISET 9
SS 10
ADM1075
TOP VIEW
(Not to Scale)
24 VEE
23 SPLYGD
22 ADC_AUX
21 PWRGD
20 SCL
19 SDAI
TIMER 11
18
SDAO
LATCH 12
17 GPO2/ALERT2
ADR 13
SHDN 14
16
15
GPO1/ALERT1/CONV
RESTART
NOTES
1. EXPOSED PAD. SOLDER THE EXPOSED PAD TO THE BOARD TO
IMPROVE THERMAL DISSIPATION. THE EXPOSED PAD CAN BE
CONNECTED TO VEE.
Figure 3. TSSOP Pin Configuration
Table 5. Pin Function Descriptions
Pin No.
Figure 4. LFCSP Pin Configuration
TSSOP LFCSP
1 25
Mnemonic
DRAIN
Description
Connect to the drain pin of the FET through a resistor. The current in this resistor is used to determine
the V DS of the MOSFET. This is used for PWRGD.
2
26
VIN
Shunt Regulated Positive Supply to Chip. Connect to the positive supply rail via a shunt resistor. A
1 μF capacitor to VEE is recommended on the VIN pin.
3
27
UVH
Undervoltage Rising Input Pin. An external resistor divider is used from the supply to this pin to allow
an internal comparator to detect if the supply is under the UVH limit.
4
28
UVL
Undervoltage Falling Input Pin. An external resistor divider is used from the supply to this pin to
allow an internal comparator to detect if the supply is under the UVL limit.
5
1
OV
Overvoltage Input Pin. An external resistor divider is used from the supply to this pin to allow an
internal comparator to detect if the supply is above the OV limit.
6
2
PLIM
The voltage on this pin is proportional to the V DS voltage of the FET. As the PLIM voltage changes, the
current limit automatically adjusts to maintain constant power across the FET.
7
3
VCAP
A capacitor with a value of 1 μF or greater should be placed on this pin to maintain good accuracy.
This is an internal regulated supply. This pin can be used as a reference to program the ISET pin
voltage.
8
4
ADC_V
This pin is used to read back the input voltage using the internal ADC. It can be connected to the OV
string or a separate divider.
9
5
ISET
This pin allows the current limit threshold to be programmed. The default limit is set when this pin is
connected directly to VCAP. Alternatively, using a resistor divider from VCAP, the current limit can be
adjusted to achieve a user defined sense voltage. An external reference can also be used.
10
6
SS
A capacitor is used on this pin to set the inrush current soft start ramp profile. The voltage on the soft
start pin controls the current sense voltage limit, allowing control over the inrush current profile.
11
7
TIMER
Timer Pin. An external capacitor, C TIMER , sets an initial timing cycle delay and a fault delay. The GATE
pin turns off when the voltage on the TIMER pin exceeds the upper threshold.
12
8
LATCH
This pin signals the device latching off after an overcurrent fault. This pin is also used to configure the
desired retry scheme. See the Hot Swap Fault Retry section for additional details.
13
9
ADR
PMBus Address Pin. This pin can be tied low, tied to VCAP, left floating, or tied low through a resistor
to set four different PMBus addresses.
Rev. C | Page 11 of 52
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