参数资料
| 型号： | ADM691SQ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 6/16页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR MPU 4.65V 16CDIP |
| 标准包装： | 25 |
| 类型： | 备用电池电路 |
| 监视电压数目： | 1 |
| 输出： | 开路漏极，推挽式 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 35 ms |
| 电压 - 阀值： | 4.65V |
| 工作温度： | -55°C ~ 125°C |
| 安装类型： | 通孔 |
| 封装/外壳： | 16-CDIP（0.300"，7.62mm） |
| 供应商设备封装： | 16-CDIP |
| 包装： | 管件 |
ADM690–ADM695
POWER FAIL RESET OUTPUT
RESET is an active low output which provides a RESET signal
to the Microprocessor whenever V CC is at an invalid level. When
V CC falls below the reset threshold, the RESET output is forced
low. The nominal reset voltage threshold is 4.65 V (ADM690/
ADM691/ADM694/ADM695) or 4.4 V (ADM692/ADM693).
Watchdog Timer RESET
The watchdog timer circuit monitors the activity of the micro-
processor in order to check that it is not stalled in an indefinite
loop. An output line on the processor is used to toggle the
Watchdog Input (WDI) line. If this line is not toggled within the
selected timeout period, a RESET pulse is generated. The
nominal watchdog timeout period is preset at 1.6 seconds on the
V CC
V2
V1
V2
V1
ADM690/ADM692/ADM694. The ADM691/ADM693/ADM695
may be configured for either a fixed “short” 100 ms or a “long”
1.6 second timeout period or for an adjustable timeout period.
RESET
t 1
t 1
If the “short” period is selected, some systems may be unable to
service the watchdog timer immediately after a reset, so the
ADM691/ADM693/ADM695 automatically selects the “long”
timeout period directly after a reset is issued. The watchdog
LOW LINE
t 1 = RESET TIME.
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 2. Power Fail Reset Timing
On power-up RESET will remain low for 50 ms (200 ms for
ADM694 and ADM695) after V CC rises above the appropriate
reset threshold. This allows time for the power supply and mi-
croprocessor to stabilize. On power-down, the RESET output
remains low with V CC as low as 1 V. This ensures that the
microprocessor is held in a stable shutdown condition.
This RESET active time is adjustable on the ADM691/ADM693/
ADM695 by using an external oscillator or by connecting an
external capacitor to the OSC IN pin. Refer to Table I and
Figure 4.
The guaranteed minimum and maximum thresholds of the
ADM690/ADM691/ADM694/ADM695 are 4.5 V and 4.73 V,
timer is restarted at the end of reset, whether the reset was
caused by lack of activity on WDI or by V CC falling below the
reset threshold.
The normal (short) timeout period becomes effective following
the first transition of WDI after RESET has gone inactive. The
watchdog timeout period restarts with each transition on the
WDI pin. To ensure that the watchdog timer does not time out,
either a high-to-low or low-to-high transition on the WDI pin
must occur at or less than the minimum timeout period. If WDI
remains permanently either high or low, reset pulses will be
issued after each “long” timeout period (1.6 s). The watchdog
monitor can be deactivated by floating the Watchdog Input
(WDI) or by connecting it to midsupply.
WDI
WDO
while the guaranteed thresholds of the ADM692/ADM693 are
4.25 V and 4.48 V. The ADM690/ADM691/ADM694/ADM695
is, therefore, compatible with 5 V supplies with a +10%, –5%
RESET
t 2
t 3
tolerance while the ADM692/ADM693 is compatible with 5 V
± 10% supplies. The reset threshold comparator has approxi-
t 1
t 1
t 1
mately 50 mV of hysteresis. The response time of the reset volt-
age comparator is less than 1 μ s. If glitches are present on the
V CC line which could cause spurious reset pulses, then V CC
should be decoupled close to the device.
In addition to RESET the ADM691/ADM693/ADM695 con-
tain an active high RESET output. This is the complement of
RESET and is intended for processors requiring an active high
RESET signal.
–6 –
t 1 = RESET TIME.
t 2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD.
t 3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET.
Figure 3. Watchdog Timeout Period and Reset Active
Time
REV. A
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