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参数资料
| 型号： | ADM696AR |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/12页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVISOR MPU 100MA 16SOIC |
| 标准包装： | 47 |
| 类型： | 备用电池电路 |
| 监视电压数目： | 1 |
| 输出： | 推挽式，推挽式 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 35 ms |
| 电压 - 阀值： | 1.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 管件 |
ADM696/ADM697
Replacing the Back-Up Battery
When changing the back-up battery with system power on, spu-
rious resets can occur when the battery is removed. This occurs
because the leakage current flowing out of the V BATT pin will
charge up the stray capacitance. If the voltage on V BATT reaches
within 50 mV of V CC , a reset pulse is generated.
If spurious resets during battery replacement are acceptable,
then no action is required. If not, then one of the following solu-
tions should be considered:
1. A capacitor from V BATT to GND. This gives time while the
capacitor is charging up to change the battery. The leakage
current will charge up the external capacitor towards the
V CC level. The time taken is related to the charging current,
the size of external capacitor and the voltage differential be-
tween the capacitor and the charging voltage supply.
t = C EXT × V DIFF /I
The maximum leakage (charging) current is 1 μ A over tem-
perature and V DIFF = V CC V BATT . Therefore, the capacitor
size should be chosen such that sufficient time is available to
If the watchdog timer is not needed the WDI input should be
left floating.
Power Fail Detector
The Power Fail Input, PFI, monitors the input power supply via
a resistive divider network R1 and R2. This input is intended as
an early warning power fail input. The voltage on the PFI input
is compared with a precision 1.3 V internal reference. If the in-
put voltage drops below 1.3 V, a power fail output (PFO) signal
is generated. This warns of an impending power failure and may
be used to interrupt the processor so that the system may be
shut down in an orderly fashion. The resistors in the sensing
network are ratioed to give the desired power fail threshold volt-
age V T . The threshold should be set at a higher voltage than the
RESET threshold so that there is sufficient time available to
complete the shutdown procedure before the processor is
RESET and power is lost.
+5V
make the battery replacement.
C EXT = T REQD (1 μ A/ ( V CC – V BATT ))
R3
R1
PFI
V CC
V OUT
μP POWER
CMOS RAM
POWER
If a replacement time of 5 s is allowed and assuming a V CC
of 4.5 V and a V BATT of 3 V,
RESET
R4
R2
LL IN
ADM696
μP SYSTEM
GND
C EXT = 3.33 μ F
2. A resistor from V BATT to GND. This will prevent the voltage
on V BATT from rising to within 50 mV of V CC during battery
BATTERY
+
V BATT
RESET
PFO
WDI
μP RESET
μP NMI
I/O LINE
replacement.
R = ( V CC – 50 mV )/1 μ A
Note that the resistor will discharge the battery slightly.
With a V CC supply of 4.5 V, a suitable resistor is 4.3 M ? .
With a 3 V battery, this will draw around 700 nA. This will
be negligible in most cases.
TYPICAL APPLICATIONS
ADM696
Figure 18 shows the ADM696 in a typical power monitoring,
battery backup application. V OUT powers the CMOS RAM.
Under normal operating conditions with V CC present, V OUT is
Figure 18a. ADM696 Typical Application Circuit A
Figure 18b shows a similar application for the ADM696 but in
this case the PFI input monitors the unregulated input to the
7805 voltage regulator. This gives an earlier warning of an im-
pending power failure. It is useful with processors operating at
low speeds or where there are a significant number of house-
keeping tasks to be completed before the power is lost.
INPUT
POWER
internally connected to V CC . If a power failure occurs, V CC will
7805
0.1μF
0.1μF
decay and V OUT will be switched to V BATT , thereby maintaining
V CC
V
power for the CMOS RAM.
Power Fail RESET
The V CC power supply is also monitored by the Low Line In-
R1
3V
BATTERY
BATT
ON
BATT
ADM696
V
OUT
V CC
CMOS
RAM
put, LL IN . A RESET pulse is generated when LL IN falls below
1.3 V. RESET will remain low for 50 ms after LL IN returns
above 1.3 V. This allows for a power-on reset and prevents re-
R2
PFI
GND
WDI
A0–A15
I/O LINE
μP
POWER
peated toggling of RESET if the V CC power supply is unstable.
Resistors R3 and R4 should be chosen to give the desired V CC
R3
NC
OSC IN
OSC SEL
PFO
RESET
NMI
RESET
μP
reset threshold.
LL
IN
Watchdog Timer
R4
RESET
LOW LINE
WDO
The Watchdog Timer Input (WDI) monitors an I/O line from
the μ P system. This line must be toggled once every 1.6 s to
verify correct software execution. Failure to toggle the line indi-
cates that the μ P system is not correctly executing its program
and may be tied up in an endless loop. If this happens, a reset
pulse is generated to initialize the processor.
–10 –
SYSTEM STATUS
INDICATORS
Figure 18b. ADM696 Typical Application Circuit B
REV. 0
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| ADM696ARZ | 功能描述:IC SUPERVISOR MPU 100MA 16SOIC RoHS:是 类别:集成电路 (IC) >> PMIC - 监控器 系列:- 标准包装:100 系列:- 类型:简单复位/加电复位 监视电压数目:1 输出:开路漏极，开路漏极 复位:高有效/低有效 复位超时:最小为 250 ms 电压 - 阀值:4.37V，4.62V 工作温度:0°C ~ 70°C 安装类型:表面贴装 封装/外壳:8-SOIC（0.154"，3.90mm 宽） 供应商设备封装:8-SOIC 包装:管件 产品目录页面:1337 (CN2011-ZH PDF) |
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