参数资料
型号: ADM696AR
厂商: Analog Devices Inc
文件页数: 6/12页
文件大小: 0K
描述: IC SUPERVISOR MPU 100MA 16SOIC
标准包装: 47
类型: 备用电池电路
监视电压数目: 1
输出: 推挽式,推挽式
复位: 高有效/低有效
复位超时: 最小为 35 ms
电压 - 阀值: 1.3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 管件
ADM696/ADM697
Table I. ADM696, ADM697 Reset Pulse Width and Watchdog Timeout Selections
Watchdog Timeout Period
Reset Active Period
OSC SEL
OSC IN
Normal
Immediately After Reset
Low
Low
Floating or High
Floating or High
External Clock Input
External Capacitor
Low
Floating or High
1024 CLKS
400 ms × C/47 pF
100 ms
1.6 s
4096 CLKS
1.6 s × C/47 pF
1.6 s
1.6 s
512 CLKS
200 ms × C/47 pF
50 ms
50 ms
NOTE
With the OSC SEL pin low, OSC IN can be driven by an external clock signal, or an external capacitor can be connected between OSC IN and GND. The nominal
internal oscillator frequency is 10.24 kHz. The nominal oscillator frequency with external capacitor is: F OSC (Hz) = 184,000/C (pF).
8
OSC SEL
WDI
ADM69x
7
OSC IN
WDO
C OSC
t 2
t 3
Figure 4b. External Capacitor
RESET
t 1
t 1
t 1
NC
8
OSC SEL
ADM69x
t 1 = RESET TIME
t 2 = NORMAL (SHORT) WATCHDOG TIMEOUT PERIOD
t 3 = WATCHDOG TIMEOUT PERIOD IMMEDIATELY FOLLOWING A RESET
NC
7
OSC IN
Figure 3. Watchdog Timeout Period and Reset Active Time
Figure 4c. Internal Oscillator (1.6 s Watchdog)
The watchdog timeout period defaults to 1.6 s and the reset
pulse width defaults to 50 ms but these times to be adjusted as
NC
8
OSC SEL
shown in Table I. Figure 4 shows the various oscillator configu-
rations which can be used to adjust the reset pulse width and
watchdog timeout period.
The internal oscillator is enabled when OSC SEL is high or
floating. In this mode, OSC IN selects between the 1.6 second
and 100 ms watchdog timeout periods. In either case, immedi-
ately after a reset the timeout period is 1.6 s. This gives the mi-
7
OSC IN
ADM69x
croprocessor time to reinitialize the system. If OSC IN is low,
then the 100 ms watchdog period becomes effective after the
first transition of WDI. The software should be written such
that the I/O port driving WDI is left in its power-up reset state
until the initialization routines are completed and the micropro-
cessor is able to toggle WDI at the minimum watchdog timeout
period of 70 ms.
Figure 4d. Internal Oscillator (100 ms Watchdog)
Watchdog Output ( WDO )
The Watchdog Output WDO provides a status output which
goes low if the watchdog timer “times out” and remains low
until set high by the next transition on the watchdog input.
WDO is also set high when LL IN goes below the reset threshold.
CLOCK
8
OSC SEL
ADM69x
0 TO 250kHz
7
OSC IN
Figure 4a. External Clock Source
–6 –
REV. 0
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