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| 型号： | ADM8697ARWZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/13页 |
| 文件大小： | 0K |
| 描述： | IC SUPERVSR MPU ADJ/RESET 16SOIC |
| 标准包装： | 47 |
| 类型： | 备用电池电路 |
| 监视电压数目： | 1 |
| 输出： | 推挽式，推挽式 |
| 复位： | 高有效/低有效 |
| 复位超时： | 最小为 35 ms |
| 电压 - 阀值： | 1.3V |
| 工作温度： | -40°C ~ 85°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 16-SOIC（0.295"，7.50mm 宽） |
| 供应商设备封装： | 16-SOIC W |
| 包装： | 管件 |
ADM8696/ADM8697
PIN FUNCTION DESCRIPTION
Pin No.
Mnemonic
ADM8696 ADM8697 Function
V CC
V BATT
V OUT
3
1
2
3
—
—
Power Supply Input +3 V to +5 V.
Backup Battery Input.
Output Voltage, V CC or V BATT is internally switched to V OUT depending on which is at
the highest potential. When V CC is higher than V BATT and LL IN is higher than the reset
threshold, V CC is switched to V OUT . When V CC is lower than V BATT and LL IN is below the
reset threshold, V BATT is switched to V OUT . V OUT can supply up to 100 mA to power CMOS
RAM. Connect V OUT to V CC if V OUT and V BATT are not used.
GND
RESET
4
15
5
15
0 V. Ground reference for all signals.
Logic Output. RESET goes low whenever LL IN falls below 1.3 V and remains low for 50 ms
after LL IN goes above 1.3 V. RESET also goes low for 50 ms if the watchdog timer is en-
abled but not serviced within its timeout period. The RESET pulse width can be adjusted as
shown in Table I.
WDI
11
11
Watchdog Input, WDI is a three level input. If WDI remains either high or low for longer
than the watchdog timeout period, RESET pulses low and WDO goes low. The timer resets
with each transition at the WDI input. The watchdog timer is disabled when WDI is left
floating or is driven to midsupply.
PFI
9
9
Power Fail Input. PFI is the noninverting input to the Power Fail Comparator when PFI is
less than 1.3 V, PFO goes low. Connect PFI to GND or V OUT when not used. See Figure 1.
PFO
10
10
Power Fail Output. PFO is the output of the Power Fail Comparator. It goes low when PFI
is less than 1.3 V. The comparator is turned off and PFO goes low when V CC is below
V BATT .
CE IN
CE OUT
—
—
13
12
Logic Input. The input to the CE gating circuit. Connect to GND or V OUT if not used.
Logic Output. CE OUT is a gated version of the CE IN signal. CE OUT tracks CE IN when LL IN
is above 1.3 V. If LL IN is below 1.3 V, CE OUT is forced high.
BATT ON
5
—
Logic Output. BATT ON goes high when V OUT is internally switched to the V BATT input.
It goes low when V OUT is internally switched to V CC . The output typically sinks 7 mA and
can directly drive the base of an external PNP transistor to increase the output current above
the 100 mA rating of V OUT .
LOW LINE 6
6
Logic Output. LOW LINE goes low when LL IN falls below 1.3 V. It returns high as soon as
LL IN rises above 1.3 V.
RESET
OSC SEL
16
8
16
8
Logic Output. RESET is an active high output. It is the inverse of RESET .
Logic Oscillator Select Input. When OSC SEL is unconnected or driven high, the internal
oscillator sets the reset time delay and watchdog timeout period. When OSC SEL is low, the
external oscillator input, OSC IN, is enabled. OSC SEL has a 3 μ A internal pull-up. See
Table I and Figure 4.
OSC IN
7
7
Logic Oscillator Input. When OSC SEL is low, OSC IN can be driven by an external clock
to adjust both the reset delay and the watchdog timeout period. The timing can also be
adjusted by connecting an external capacitor to this pin. See Table I and Figure 4. When
OSC SEL is high or floating, OSC IN selects between fast and slow watchdog timeout periods.
WDO
14
14
Logic Output. The Watchdog Output, WDO , goes low if WDI remains either high or low
for longer than the watchdog timeout period. WDO is set high by the next transition at
WDI. If WDI is unconnected or at midsupply, WDO remains high. WDO also goes high
when LOW LINE goes low.
NC
LL IN
12
13
2
4
No Connect. It should be left open.
Voltage Sensing Input. The voltage on the low line input, LL IN , is compared with a 1.3 V
reference voltage. This input is normally used to monitor the power supply voltage. The
output of the comparator generates a LOW LINE output signal. It also generates a
RESET/ RESET output. The comparator output also controls the battery switchover circuitry.
TEST
—
1
This is a special test pin using during device manufacture. It should be connected to GND.
REV. A
–4 –
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