参数资料
型号: ADM8697ARWZ
厂商: Analog Devices Inc
文件页数: 7/13页
文件大小: 0K
描述: IC SUPERVSR MPU ADJ/RESET 16SOIC
标准包装: 47
类型: 备用电池电路
监视电压数目: 1
输出: 推挽式,推挽式
复位: 高有效/低有效
复位超时: 最小为 35 ms
电压 - 阀值: 1.3V
工作温度: -40°C ~ 85°C
安装类型: 表面贴装
封装/外壳: 16-SOIC(0.295",7.50mm 宽)
供应商设备封装: 16-SOIC W
包装: 管件
ADM8696/ADM8697
CE Gating and RAM Write Protection (ADM8697)
The ADM8697 contains memory protection circuitry that
ensures the integrity of data in memory by preventing write
operations when LL IN is below the threshold voltage. When
LL IN is greater than 1.3 V, CE OUT is a buffered replica of CE IN ,
with a 2 ns propagation delay. When LL IN falls below the 1.3 V
can be chosen such that the voltage at PFI falls below 1.3 V
several milliseconds before the +5 V power supply falls below
the reset threshold. PFO is normally used to interrupt the
microprocessor so that data can be stored in RAM and the shut-
down procedure executed before power is lost.
threshold, an internal gate forces CE OUT high, independent of
CE IN .
INPUT
POWER
ADM869x
CE OUT typically drives the CE, CS or Write input of battery
backed up CMOS RAM. This ensures the integrity of the data
in memory by preventing write operations when V CC is at an in-
valid level.
R1
R2
POWER
FAIL
INPUT
1.3V
PFO
POWER
FAIL
OUTPUT
ADM8697
Figure 7. Power Fail Comparator
CE IN
CE OUT
Table II. Input and Output Status In Battery Backup Mode
LL IN LOW = 0
LL IN OK = 1
Figure 5. Chip Enable Gating
Signal
V OUT
RESET
Status
(ADM8696) V OUT is connected to V BATT via an
internal PMOS switch.
Logic low.
LL IN
V2
V1
V2
V1
RESET
Logic high. The open circuit output voltage is
equal to V OUT .
LOW LINE
Logic low.
RESET
t 1
t 1
BATT ON
(ADM8696) Logic high. The open circuit volt-
age is equal to V OUT .
LOW LINE
CE IN
CE OUT
t 1 = RESET TIME
V1 = RESET VOLTAGE THRESHOLD LOW
V2 = RESET VOLTAGE THRESHOLD HIGH
HYSTERESIS = V2–V1
Figure 6. Chip Enable Timing
Power Fail Warning Comparator
An additional comparator is provided for early warning of fail-
ure in the microprocessor’s power supply. The Power Fail Input
(PFI) is compared to an internal +1.3 V reference. The Power
Fail Output ( PFO ) goes low when the voltage at PFI is less than
1.3 V. Typically PFI is driven by an external voltage divider
which senses either the unregulated dc input to the system’s 5 V
regulator or the regulated 5 V output. The voltage divider ratio
REV. A
–7 –
WDI
WDO
PFI
PFO
CE IN
CE OUT
OSC IN
OSC SEL
WDI is ignored. It is internally disconnected
from the internal pull-up resistor and does not
source or sink current as long as its input voltage
is between GND and V OUT . The input voltage
does not affect supply current.
Logic high. The open circuit voltage is equal to
V OUT .
The Power Fail Comparator is turned off and
has no effect on the Power Fail Output.
Logic low.
CE IN is ignored. It is internally disconnected
from its internal pull-up and does not source or
sink current as long as its input voltage is be-
tween GND and V OUT . The input voltage does
not affect supply current.
Logic high. The open circuit voltage is equal to
V OUT .
OSC IN is ignored.
OSC SEL is ignored.
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