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参数资料
| 型号： | ADMC200 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Motion Coprocessor(动作协处理器) |
| 中文描述： | 运动协处理器（动作协处理器） |
| 文件页数： | 12/12页 |
| 文件大小： | 334K |
| 代理商： | ADMC200 |
ADMC200
REV. A
–12–
Bit 0, 1 Reserved for future use. Always write 0 to these bits.
Bit 3
Channel U Conversion Enable. If Bit 3 is set to 1, then
Channel U will be converted along with V, W and/or
AUX. This bit selects three-/three-phase mode.
Bit 4
Aux Channel Conversion Enable. If Bit 4 is set to
1, then the AUX input will be converted along with
the channels V, W and/or U.
Bit 5
If Bit 5 = 1, then the external clock will be divided by
two to derive the system clock. If the external clock
frequency is greater than 12.5 MHz, then this bit must
be set.
Bit 6
Park Interrupt Enable. This bit allows interrupts to
be generated when the Park rotation is completed.
Bit 7
ADC Interrupt Enable. This bit allows interrupts to
be generated via the
IRQ
pin when the analog-to-
digital conversion process is complete.
Bit 8
IRQ
Pin Format—Edge or Level Interrupt Selection.
If Bit 8 is set to 0, then an interrupt will cause a pulse
of one system clock to be generated on the
IRQ
pin.
If Bit 8 is set to 1, then an interrupt causes the
IRQ
output to go LOW (logic 0). The
IRQ
output pin
will remain LOW until the SYSSTAT register is read.
Bit 10
If Bit 10 is set to 1, then the reverse Park transforma-
tion will be formed in 3/3 mode. For Forward
transformations, this bit must be set to 1.
Table VII. System Status Register (SYSSTAT)
1
RESET
Default
Bit
Function
0
A/D Conversion
Completion Interrupt
(1 = True)
Vector Transformation
Completion Interrupt
(1 = True)
Rotation Results are Valid
(1 = Valid)
IRQ
Generated from This
Device (1 = True)
0
1
0
4
X
2
0
11
NOTES
1
Reading this register clears the interrupt status flags Bits 0, 1 and 11.
2
Undefined until the first Vector Transformation has started
Bit 0
A/D Conversion Completion Interrupt. This register
is set to 1 when the A/D conversion process has com-
pleted and ADC interrupts have been enabled in the
SYSCTRL register.
Bit 1
Interrupt Status. This register is set to 1 when the
Vector Transformation is completed and the Vector
Transformation completion interrupts have been
enabled.
Bit 4
This bit is set to 1 when the rotation results are valid.
Bit 11
If any interrupt source on the ADMC200 occurs, then
this bit is set to 1.
C
P
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
68-Lead Plastic Leaded Chip Carrier (PLCC)
(P-68A)
9
IDPIN 1
10
61
60
26
27
44
43
TOP VIEW
(PINS DOWN)
0.995 (25.27)
0.954 (24.23)
0.019 (0.48)
0.017 (0.43)
0.050
(1.27)
TYP
0.925 (23.50)
0.895 (22.73)
0.029 (0.74)
0.027 (0.69)
0.104 (2.64) TYP
0.175 (4.45)
0.169 (4.29)
BOTTOM VIEW
(PINS UP)
PIN 1
IDENTIFIER
相关PDF资料 |
PDF描述 |
|---|---|
| ADMC201AP | Motion Coprocessor |
| ADMC201 | Motion Coprocessor(动作协处理器) |
| ADMC300 | High Performance DSP-Based Motor Controller |
| ADMC300-PB | High Performance DSP-Based Motor Controller |
| ADMC300BST | High Performance DSP-Based Motor Controller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADMC200AP | 制造商:AD 制造商全称:Analog Devices 功能描述:Motion Coprocessor |
| ADMC201 | 制造商:AD 制造商全称:Analog Devices 功能描述:Motion Coprocessor |
| ADMC201AP | 制造商:Analog Devices 功能描述: |
| ADMC300 | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
| ADMC300-ADVEVALKIT | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
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