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参数资料
| 型号： | ADMC200 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | Motion Coprocessor(动作协处理器) |
| 中文描述： | 运动协处理器（动作协处理器） |
| 文件页数： | 2/12页 |
| 文件大小： | 334K |
| 代理商： | ADMC200 |
ADMC200–SPECIFICATIONS
Parameter
(V
DD
= +5 V
6
5%; AGND = DGND = 0 V; REFIN = 2.5 V; External Clock =
12.5 MHz; T
A
= –40
8
C to +85
8
C unless otherwise noted)
ADMC200AP Units
Conditions/Comments
ANALOG-TO-DIGITAL CONVERTER
1
Resolution
Relative Accuracy
Differential Nonlinearity
Bias Offset Error
Bias Offset Match
Full-Scale Error
Full-Scale Error Match
Conversion Time/Channel
Signal-to-Noise Ratio (SNR)
2
Channel-to-Channel Isolation
Two-/Three-Phase Mode
Three-/Three-Phase Mode
ANALOG INPUTS
Input Voltage Level
Analog Input Current
Input Capacitance
11
±
2
±
2
±
5
4
±
5
4
40
60
Bits
LSB max
LSB max
LSB max
LSB max
LSB max
LSB max
System CLK Cycles
dB min
Twos Complement Data Format
Integral Nonlinearity
No Missing Codes Guaranteed
Any Channel
Between Channels
Any Channel
Between Channels
f
IN
= 600 Hz Sine Wave, f
SAMPLE
= 55 kHz, 600 Hz
Sine Wave Applied to Unselected Channels
–60
–55
dB max
dB max
0–5
100
10
Volts
μ
A max
pF typ
TRACK AND HOLD
Aperture Delay
Aperture Time Delay Match
SHA Acquisition Time
Droop Rate
REFERENCE INPUT
Voltage Level
Reference Input Current
REFERENCE OUTPUT
Voltage Level
Voltage Level Tolerance
Drive Capability
200
20
20
5
ns max
ns max
System CLK Cycles
mV/ms max
Any Channel
Between Channels
2.5
50
V dc
μ
A max
2.5
±
5
±
200
Volts
% max
μ
A max
Full Load
LOGIC
V
IL
V
IH
V
OL
V
OH
Input Leakage Current
Three-State Leakage Current
Input Capacitance
0.8
2.0
0.4
4.5
1
1
20
V max
V min
V max
V min
μ
A max
μ
A max
pF typ
I
SINK
= 400
μ
A, V
DD
= 5 V
I
SOURCE
= 20
μ
A, V
DD
= 5 V
12-BIT PWM TIMERS
Resolution
Programmable Deadtime Range
Programmable Deadtime Increments
Programmable Pulse Deletion Range
Programmable Deletion Increments
Minimum PWM Frequency
12
0–10.08
2
0–10.16
1
1.5
Bits
μ
s
System CLK Cycles
μ
s
System CLK Cycle
kHz
160 ns
80 ns
Resolution Varies with PWM Switching Frequency
(10 MHz Clock: 20 kHz = 9 Bits, 10 kHz = 10 Bits,
5 kHz = 11 Bits, 2.5 kHz = 12 Bits). Higher Fre-
quencies are Available with Lower Resolution
Park & Clarke Transformation
VECTOR TRANSFORMATION
Radius Error
Angular Error
Reverse Transformation Time
Forward Transformation Time
0.7
30
37
40
% max
arc min max
System CLK Cycles
System CLK Cycles
EXTERNAL CLOCK INPUT
Range
6.25–25
MHz
If > 12.5 MHz, Then It Is Necessary to Divide Down
via SYSCTRL Register
INTERNAL SYSTEM CLOCK
Range
6.25–12.5
MHz
POWER SUPPLY CURRENT
I
DD
20
mA max
NOTES
1
Measurements made with external reference.
2
Tested with PWM Switching Frequency of 25 kHz.
Specifications subject to change without notice.
REV. A
–2–
相关PDF资料 |
PDF描述 |
|---|---|
| ADMC201AP | Motion Coprocessor |
| ADMC201 | Motion Coprocessor(动作协处理器) |
| ADMC300 | High Performance DSP-Based Motor Controller |
| ADMC300-PB | High Performance DSP-Based Motor Controller |
| ADMC300BST | High Performance DSP-Based Motor Controller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADMC200AP | 制造商:AD 制造商全称:Analog Devices 功能描述:Motion Coprocessor |
| ADMC201 | 制造商:AD 制造商全称:Analog Devices 功能描述:Motion Coprocessor |
| ADMC201AP | 制造商:Analog Devices 功能描述: |
| ADMC300 | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
| ADMC300-ADVEVALKIT | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
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