参数资料
型号: ADMC200AP
厂商: ANALOG DEVICES INC
元件分类: 微控制器/微处理器
英文描述: Motion Coprocessor
中文描述: SPECIALTY MICROPROCESSOR CIRCUIT, PQCC68
封装: PLASTIC, LCC-68
文件页数: 11/12页
文件大小: 134K
代理商: ADMC200AP
ADMC200
REV. B
11
DESCRIPTION OF THE REGISTERS
All unspecified register locations are reserved.
SYSCTRL
System Control Register (See Table V and VI)
SYSSTAT
System Status Register (See Table VII)
ADCU
These registers contain the results from the first
ADCV
three analog input channels U, V, and W. The
ADCW
output data format is twos complement and
therefore Bit 0 is always zero as the A/D
converter has 11-bit resolution.
ADCAUX
This register contains the conversion result
of the auxiliary channel.
PWMTM
PWM Master Switching Period
PWMCHA
PWM Channel A on-time
PWMCHB
PWM Channel B on-time
PWMCHC
PWM Channel C on-time
PWMDT
PWM Programmable Deadtime Value
PWMPD
PWM Programmable Pulse Deletion Value
ID/IQ
These are the results of the reverse rotation
(torque and flux components).
PHV1/2/3
These are the results from the forward
Clarke Transformation.
PHIP1/2/3
The inputs for reverse vector transformation
(Clarke and Park).
IX/IY
These registers contain the results of the Clarke
transformation that are the inputs to the reverse
Park rotation.
VX, VY
VX , VY contain the results of the forward
Park rotation.
RHOP
RHOP is the angle used during the forward vec-
tor transformation. Writing to the RHOP regis-
ter causes the forward rotation to start based on
values in RHOP, VD and VQ registers.
RHO
RHO is the angle used during the reverse vector
transformation. Writing to this register starts
the reverse rotation using the values in the
RHO, PHIP1/2/3 registers.
RHO and RHOP are unsigned ratios of 360
°
.
For example, 45 degrees would be 45/360
×
2
12
.
Table IV. Read Registers
Name
A
3
A
2
A
1
A
0
Register Function
ID/PHV1/VX
IQ/PHV2
IX/PHV3
IY/VY
0
0
0
0
0
0
0
0
1
1
1
1
1
1
1
1
0
0
0
0
1
1
1
1
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
0
1
Reverse Rotation Result (I
DS
)/Forward Result Cos +0
°
Reverse Rotation Result (I
QS
)/Forward Cos +120
°
Reverse Clarke Cos + 0
°
/Forward Result Cos +240
°
Reverse Clarke Cos +90
°
/Forward Cos +90
°
Reserved
A/D Conversion Result Channel V
A/D Conversion Result Channel W
A/D Conversion Result Auxiliary Channel
A/D Conversion Result Channel U
Reserved
Reserved
Reserved
Reserved
System Control
System Status
Reserved
ADCV
ADCW
ADCAUX
ADCU
SYSCTRL
SYSSTAT
Table V. System Control (SYSCTRL) Registers
RESET
Default
Bit
Function
0
1
3
Reserved, Must Be 0
Reserved, Must Be 0
Enables U Channel Conversion
(1 = Enable) Three/Three-Phase Mode
Enables AUX Channel Conversion
(0 = Disable, 1 = Enable)
Divide External Clock by 2
(0 = No, 1 = Yes)
Park Interrupt Enable
ADC Interrupt Enable
(0 = Disable, 1 = Enable)
IRQ
Pin Format (Edge or Level Based
Interrupt Requests) (0 = Edge)
Reverse Rotation (0 = 2/3, 1 = 3/3)
Forward Rotation (1 = Enable)
0
0
0
4
0
5
0
0
6
7
0
8
0
10
0
Bit 0, 1 Reserved for future use. Always write 0 to these bits.
Bit 3
Channel U Conversion Enable. If Bit 3 is set to 1, then
Channel U will be converted along with V, W and/or
AUX. This bit selects three-/three-phase mode.
Bit 4
Aux Channel Conversion Enable. If Bit 4 is set to
1, then the AUX input will be converted along with
the channels V, W and/or U.
Bit 5
If Bit 5 = 1, then the external clock will be divided by
two to derive the system clock. If the external clock
frequency is greater than 12.5 MHz, then this bit must
be set.
Bit 6
Park Interrupt Enable. This bit allows interrupts to
be generated when the Park rotation is completed.
Bit 7
ADC Interrupt Enable. This bit allows interrupts to
be generated via the
IRQ
pin when the analog-to-
digital conversion process is complete.
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