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参数资料
| 型号： | ADMC200AP |
| 厂商： | ANALOG DEVICES INC |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | Motion Coprocessor |
| 中文描述： | SPECIALTY MICROPROCESSOR CIRCUIT, PQCC68 |
| 封装： | PLASTIC, LCC-68 |
| 文件页数： | 12/12页 |
| 文件大小： | 134K |
| 代理商： | ADMC200AP |
ADMC200
REV. B
–
12
–
Table VII. System Status Register (SYSSTAT)
1
RESET
Default
Bit
Function
0
A/D Conversion
Completion Interrupt
(1 = True)
Vector Transformation
Completion Interrupt
(1 = True)
Rotation Results are Valid
(1 = Valid)
IRQ
Generated from This
Device (1 = True)
0
1
0
4
X
2
0
11
NOTES
1
Reading this register clears the interrupt status flags Bits 0, 1 and 11.
2
Undefined until the first Vector Transformation has started
Bit 0
A/D Conversion Completion Interrupt. This register
is set to 1 when the A/D conversion process has com-
pleted and ADC interrupts have been enabled in the
SYSCTRL register.
Bit 1
Interrupt Status. This register is set to 1 when the
Vector Transformation is completed and the Vector
Transformation completion interrupts have been
enabled.
Bit 4
This bit is set to 1 when the rotation results are valid.
Bit 11
If any interrupt source on the ADMC200 occurs, then
this bit is set to 1.
C
–
1
–
4
P
OUTLINE DIMENSIONS
Dimensions shown in inches and (mm).
68-Lead Plastic Leaded Chip Carrier (PLCC)
(P-68A)
9
IDPIN 1
10
61
60
26
27
44
43
(PINS DOWN)
0.995 (25.27)
0.954 (24.23)
0.019 (0.48)
0.017 (0.43)
0.050
(1.27)
TYP
0.925 (23.50)
0.895 (22.73)
0.029 (0.74)
0.027 (0.69)
0.104 (2.64) TYP
0.175 (4.45)
0.169 (4.29)
BOTTOM VIEW
IDPIN 1
Table VI. SYSCTRL Analog Input Channel Selection
Bit 3
Bit 4
Channels Converted
Mode
0
0
1
1
0
1
0
1
V, W (Default)
V, W, AUX
U, V, W
U, V, W, AUX
Two/Three Phase
Two/Three Phase
Three/Three Phase
Three/Three Phase
Bit 8
IRQ
Pin Format
—
Edge or Level Interrupt Selection.
If Bit 8 is set to 0, then an interrupt will cause a pulse
of one system clock to be generated on the
IRQ
pin.
If Bit 8 is set to 1, then an interrupt causes the
IRQ
output to go LOW (logic 0). The
IRQ
output pin
will remain LOW until the SYSSTAT register is read.
If Bit 10 is set to 1, then the reverse Park transforma-
tion will be formed in 3/3 mode. For Forward
transformations, this bit must be set to 1.
Bit 10
相关PDF资料 |
PDF描述 |
|---|---|
| ADMC200 | Motion Coprocessor(动作协处理器) |
| ADMC201AP | Motion Coprocessor |
| ADMC201 | Motion Coprocessor(动作协处理器) |
| ADMC300 | High Performance DSP-Based Motor Controller |
| ADMC300-PB | High Performance DSP-Based Motor Controller |
相关代理商/技术参数 |
参数描述 |
|---|---|
| ADMC201 | 制造商:AD 制造商全称:Analog Devices 功能描述:Motion Coprocessor |
| ADMC201AP | 制造商:Analog Devices 功能描述: |
| ADMC300 | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
| ADMC300-ADVEVALKIT | 制造商:AD 制造商全称:Analog Devices 功能描述:High Performance DSP-Based Motor Controller |
| ADMC300BST | 制造商:Analog Devices 功能描述:DSP Motor Controller 80-Pin TQFP 制造商:Analog Devices 功能描述:IC MOTOR CONTROLLER |
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