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参数资料
| 型号： | ADMC331 |
| 厂商： | Analog Devices, Inc. |
| 英文描述： | ECONOLINE: REC3-S_DRW(Z)/H4,H6 - Safety standards and approval: EN 60950 certified, rated for 250VAV (LVD test report)- Applied for Ul 1950 Component Recognised Certification- 3W DIP Package- 4kVDC & 6kVDC Isolation- Regulated Output- Continuous Short Circiut Protection Auto-Restarting |
| 中文描述： | 单芯片DSP的电机控制器 |
| 文件页数： | 11/36页 |
| 文件大小： | 248K |
| 代理商： | ADMC331 |
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ADMC331
–11–
REV. B
Table IV. ROM Utilities
Utility
Address
Function
PER_RST
UMASK
0x07F1
0x0DED
Reset Peripherals.
Limits Unsigned Value to
Given Range.
Facilitates User Setup of
Vector Table.
Limits Signed Value to Given
Range.
Cosine Function.
Sine Function.
Arctangent Function.
Reciprocal (1/
×
) Function.
Square Root Function.
Natural Logarithm Function.
Logarithm (Base 10) Function.
Fixed Pt. to Float Conversion.
Float to Fixed Pt. Conversion.
Floating Pt. Addition.
Floating Pt. Subtraction.
Floating Pt. Multiplication.
Floating Pt. Division.
Floating Pt. Multiply/Accumulate.
Forward/Reverse Park
Transformation.
Reverse Clark Transformation.
Forward Clark Transformation.
64 Pt. COS Table.
16 Pt. 1/
×
Table.
Unsigned Single Precision
Division (Integer).
Unsigned Single Precision
Division (Fractional).
PUT_VECTOR
0x0DF4
SMASK
0x0E06
ADMC_COS
ADMC_SIN
ARCTAN
RECIPROCAL
SQRT
LN
LOG
FLTONE
FIXONE
FPA
FPS
FPM
FPD
FPMACC
PARK
0x0E26
0x0E2D
0x0E43
0x0E65
0x0E7B
0x0EB5
0x0EB8
0x0ED4
0x0ED9
0x0EDD
0x0EEC
0x0EFC
0x0F05
0x0F26
0x0F48
REV_CLARK
FOR_CLARK
COS64
ONE_BY_X
SDIVQINT
0x0F5C
0x0F72
0x0F80
0x0FCO
0x0FD0
SDIVQ
0x0FD9
SYSTEM INTERFACE
Figure 4 shows a basic system configuration for the ADMC331,
with an external crystal and serial E
2
PROM for boot loading of
program and data memory RAM.
ADMC331
XTAL
CLKIN
DR1A
SCLK1
RFS1/
SROM
DATA
CLK
RESET
13 MHz
CLKOUT
RESET
SERIAL
E
2
PROM
Figure 4. Basic System Configuration
Clock Signals
The ADMC331 can be clocked by either a crystal or a TTL-
compatible clock signal. The CLKIN input cannot be halted,
changed during operation nor operated below the specified
minimum frequency during normal operation. If an external
clock is used, it should be a TTL-compatible signal running at
half the instruction rate. The signal is connected to the CLKIN
pin of the ADMC331. In this mode, with an external clock
signal, the XTAL pin must be left unconnected. The ADMC331
uses an input clock with a frequency equal to half the instruc-
tion rate; a 13 MHz input clock yields a 38.5 ns processor cycle
(which is equivalent to 26 MHz). Normally, instructions are
executed in a single processor cycle. All device timing is
relative to the internal instruction rate, which is indicated by
the CLKOUT signal.
Because the ADMC331 includes an on-chip oscillator feedback
circuit, an external crystal may be used instead of a clock
source, as shown in Figure 4. The crystal should be connected
across the CLKIN and XTAL pins, with two capacitors as
shown in Figure 4. A parallel-resonant, fundamental frequency,
microprocessor-grade crystal should be used. A clock output
signal (CLKOUT) is generated by the processor at the processor’s
cycle rate of twice the input frequency. This output can be
enabled and disabled by the CLKODIS bit of the SPORT0
Autobuffer Control Register, DM[0x3FF3]. However, extreme
care must be exercised when using this bit since disabling
CLKOUT effectively disables all motor control peripherals,
except the watchdog timer.
Reset
The
RESET
signal initiates a master reset of the ADMC331.
The
RESET
signal must be asserted during the power-up se-
quence to assure proper initialization.
RESET
during initial
power-up must be held long enough to allow the internal clock
to stabilize. If
RESET
is activated any time after power-up, the
clock continues to run and does not require stabilization time.
The power-up sequence is defined as the total time required for
the crystal oscillator circuit to stabilize after a valid V
DD
is ap-
plied to the processor, and for the internal phase-locked loop
(PLL) to lock onto the specific crystal frequency. A minimum
of 2000 CLKIN cycles ensures that the PLL has locked, but
does not include the crystal oscillator start-up time. During this
power-up sequence, the
RESET
signal should be held low. On
any subsequent resets, the
RESET
signal must meet the mini-
mum pulsewidth specification, t
RSP
.
If an RC circuit is used to generate the
RESET
signal, the use of
an external Schmitt trigger is recommended.
The master reset sets all internal stack pointers to the empty
stack condition, masks all interrupts, initializes DSP core regis-
ters and performs a full reset of all of the motor control periph-
erals. When the
RESET
line is released, the first instruction is
fetched from internal program memory ROM at location 0x0800.
The internal monitor code at this location then commences the
boot-loading sequence over the serial port, SPORT1. A soft-
ware controlled full peripheral reset is achieved by toggling the
DSP FL2 flag from 1 to 0 to 1 again.
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